JP2890936B2 - Word synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital radio communication system used in the field of radio communication, and more particularly to a word of a code error correction communication system in a multilevel QAM (quadrature amplitude modulation) digital radio communication using a code error correction circuit. Related to the synchronization method.

[0002]

2. Description of the Related Art Heretofore, this type of word synchronization system has a first
As a method, there is a method in which an error correction code that can be used inside differential logic is used, hunting is performed by a syndrome, and synchronization is established. As a second method, a method of multiplexing a synchronizing signal into a signal sequence independent of the pull-in phase in 16 or more QAMs has been adopted.

[0003]

In the above-mentioned first system, it is necessary to use a code which is not affected by the pull-in phase of the reproduced carrier wave, that is, a code which can be used inside the differential logic. Problem. Further, the second method has a problem that it cannot be applied to 4PSK. SUMMARY OF THE INVENTION An object of the present invention is to provide a word synchronization system for realizing word synchronization of an error correction block code without restricting a code in a multilevel QAM and a polyphase PSK modulation / demodulation system.

[0004]

According to the word synchronizing method of the present invention, the transmitting side is provided with a combination of N codes F1 to F in which the order of the codes is not affected by the synchronization pull-in phase of the reproduced carrier.
N having means for forming a synchronization signal by discretely and periodically multiplexing N with the block length of the block code to form a synchronization signal. On the receiving side, means for establishing synchronization with the synchronization signal; It has means for performing a block code error correction decoding operation.

[0005]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a main part of a transmitting / receiving apparatus in a 4PSK digital wireless communication system according to the present invention.
On the transmitting side, as shown in FIG. 3 (a), four columns of binary signals input from the input terminal 1 and the input terminal 2 have four symbols F1 to F4 whose order does not change due to phase uncertainty. Signal multiplexing circuit 10 for multiplexing as a synchronization signal,
A code error correction coding circuit 11 which receives an output of the synchronization signal multiplexing circuit 10 and performs a predetermined error correction coding operation in synchronization with the synchronization signal 3 which is an output of the synchronization signal multiplexing circuit 10; And a modulator 12 that receives an output of the code error correction encoding circuit 11, performs predetermined modulation, and outputs a modulated wave to the output terminal 4.

As shown in FIG. 1B, a receiving side receives a modulated wave transmitted from a transmitting side at an input terminal 5, performs a predetermined demodulation, and outputs a demodulated signal. A synchronization circuit 21 for establishing synchronization with the synchronization multiplexed on the transmission side and outputting a synchronization signal 6; a code error correction decoding circuit 22 for receiving the demodulated signal and the synchronization signal and performing a code error correction decoding operation; Contains. The output of the code error correction decoding circuit 22 is output to signal output terminals 8 and 9.

Next, the operation will be described with reference to a time chart shown in FIG. The figure shows the code error correction coding circuit 1 of FIG.
1 shows an output of the first signal or an input signal of the code error correction decoding circuit 22. In addition, the circles indicate four codes F1 to F4 whose order does not change due to phase uncertainty, and these four codes are multiplexed discretely and periodically in synchronization with an error correction block. .

Next, examples of codes F1 to F4 whose order does not change due to the four phase uncertainties used here will be described with reference to FIGS. 3 and 4. FIG. In FIG. 3, the arrangement of the codes on the phase plane in the modulator output of the four-phase PSK signal is shown by a solid line, and the four phases of the demodulator in which the reproduced carrier is locked are shown by broken lines.

FIG. 4 shows to which phase the modulator input undergoes code conversion for each of the four pull-in phases shown in FIG. From FIG. 4, for example, when a set of 0, 1, 2, 3 is used as a frame synchronization signal in this order, the synchronization code is 0-1-2-3, 3- at each synchronization pull-in phase in the demodulator. 0-1-2, 2-3-3-0-1,
1-2-3-0, and the code order is 0-1-
2-3 and affected by the pull-in phase
It will be understood that it is only what the starting sign is.

[0010]

As described above, according to the present invention, a code whose order is not affected by the phase uncertainty of the reproduced carrier wave is periodically multiplexed in synchronization with the error correction block code.
Since this is used as a synchronization signal, it can be used inside a differential logic circuit. Also, by sharing with an appropriate phase lock-in determination method after synchronization is established, it is possible to use a block code that is affected by the lock-in phase of the recovered carrier,
In addition, there is an effect that can be applied to 4PSK.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are block diagrams of respective transmitting / receiving sections for executing a word synchronization method according to the present invention.

FIG. 2 is a time chart showing the operation.

FIG. 3 is a diagram illustrating a code arrangement of a four-phase PSK modulation method and a synchronization pull-in phase of a reproduced carrier on a phase plane.

FIG. 4 is a diagram showing code conversion that a demodulation code receives according to a synchronization pull-in phase of a reproduced carrier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Synchronous signal multiplexing circuit 11 Code error correction coding circuit 12 Modulator 20 Demodulator 21 Synchronous circuit 22 Code error correction decoding circuit

Claims (1)

(57) [Claims] 1. In a communication system to which block code error correction is applied in a multi-phase PSK or multi-level QAM communication system, a transmitting side has N number of codes whose order of codes is not affected by a synchronization pull-in phase of a reproduced carrier. The code combinations F1 to FN are
Means for forming a synchronization signal by multiplexing discretely and periodically in synchronization with the block length of the block code, means for establishing synchronization with the synchronization signal on the receiving side,
A word synchronization system comprising means for performing a block code error correction decoding operation based on the result.