JPH09214461A - Cross polarization transmitter-receiver for digital multiplex radio - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of interference/compensation functions by controlling the sampling timing of an identification signal becoming the reference of the extraction of an error signal with the output result of a lock phase detection circuit and shifting the phase of a sampling clock. SOLUTION: The demodulated base band signal of an H-polarized wave is inputted to the cross polarized wave interference/compensation circuit 20 of a V-polarized wave-side through a cable 40 after it is converted into a digital signal by A/D conversion circuits 901 and 902. The sampling clock in the A/D conversion circuits 901 and 902 are generated into optimum phase control signals in a clock phase detector 801 based on digital data after A/D conversion. A clock phase adjustment circuit 802 phase-shifts the phase of the reproduced clock CK1 from the oscillator 30 of the V-polarized wave-side based on the control signals and controls the sample timing of the input analog signal of the cross polarized wave interference/compensation circuit 20. Thus, the maximum interference/compensation functions can be brought out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross polarization transmission system (co-channel system) for digital multiplex radio, and more particularly to a digital multiplex radio with an improved cross polarization interference compensation circuit for compensating for mutual interference between cross polarizations. Cross polarization transmission receiver.

[0002]

2. Description of the Related Art In digital wireless communication lines, it is desired to further increase the transmission capacity and improve the effective use of frequencies. In order to meet this demand, a cross polarization transmission system has been adopted.

The cross polarization transmission system is a system for transmitting signals by using horizontal (H) polarization and vertical (V) polarization, which are orthogonal to each other, as carrier waves. However, in this method, the received data may be adversely affected by mutual interference between the horizontal (H) polarized wave and the vertical (V) polarized wave.

Therefore, in order to compensate for this interference, a cross polarization interference compensating circuit is indispensable, and it is necessary to improve the compensation capability of the cross polarization interference compensating circuit and perform control so as to keep the compensation amount to the maximum. To be done.

FIG. 8 is a block diagram showing the configuration of a digital multiplex radio cross polarization transmission receiver including a conventional cross polarization interference compensation circuit. In the figure, A is a V (vertical) polarization signal side demodulation circuit, and B is an H (horizontal) polarization signal side demodulation circuit.

The respective demodulation circuits are basically the same circuit, and demodulators (DEM) 60, 61 demodulate the respective multi-level QAM signals into baseband signals for Q channel and I channel. The demodulated baseband signals for the Q channel and the I channel are respectively A / D converter 70
1, 702 and 711, 712 are converted to digital signals and then transversal equalizer (TRV)
Equalized at 10, 11.

Further, the demodulated baseband signals on the V polarization side and the H polarization side have different sides (from the V polarization side to the H polarization side and from the H polarization side to the V polarization side). 2) transmitted by cables 40, 41. Then, the signals are input to the cross polarization interference compensation circuits (XPIC) 20 and 21 on different sides.

The configurations of the cross polarization interference compensation circuits 20 and 21 are well known, and a transversal equalizer (TRV) 1 is used.
Like 0 and 11, it has a transversal filter, and the coefficient of this tap is controlled by an error signal.

Cross polarization interference compensation circuit (XPIC) 20,
The input signal to the A.D.
A / D converter 90 equivalent to 702 and 711, 712
1, 902 and 911, 912 are converted into digital signals.

Here, the A / D converters 701, 702 and 711, 712 and the A / D converters 901, 902 and 9 are used.
11, 912 are operated at the timing of the fixed clock signals CK1 and CK2 from the oscillators 30 and 31, respectively.

Therefore, in the conventional circuit shown in FIG.
In order to optimize the sampling timing of the demodulated V polarization side and H polarization side baseband signals input to the D / D converters 901, 902 and 911, 912, the lengths of the cables 40, 41 are adjusted. The delay of the baseband signal is set.

As a result, the cross polarization interference compensation circuit (XP
IC) 20 and 21 are H-polarized waves on different sides, V
Correlation detection with V-polarized and H-polarized signals leaking to the polarized wave side is performed. Next, in the adders 50 and 51, the correlation-detected values are added in antiphase to the data after equalization to minimize the polarization interference amount as the final demodulated data V _I , V _Q , H _I , and H _Q. Controlled to be.

[0013]

Here, as shown in FIG. 8, in the conventional cross polarization interference compensating circuits 20 and 21, the inputs are first input to the A / D converters 901 and 902.
At 911 and 912, a fixed timing clock is used for operation.

For this reason, the baseband signals on the different sides are delayed by a fixed cable length to adjust the sampling timing. However, there is a possibility that the sampling timing is deviated from the optimum point due to the variation in the delay depending on the cable length, the effective correlation detection becomes difficult, and the interference compensation function deteriorates.

Therefore, an object of the present invention is to provide a cross-polarization transmission receiver of digital multiplex radio using a cross-polarization interference compensation circuit which solves the problem that the interference compensation function deteriorates.

Further, according to the present invention, the sampling timing of the input signal of the A / D converter placed on the input side of the cross polarization interference compensation circuit can be operated so that the amount of interference contained in the output data is minimized. Another object of the present invention is to provide a cross-polarization transmission receiver for digital multiplex radio.

[0017]

A cross-polarization transmission receiver of a digital multiplex radio according to claim 1 for solving the above-mentioned problems of the present invention is transmitted by vertical polarization and horizontal polarization orthogonal to each other. In a digital multi-radio cross polarization transmission receiver for receiving a multilevel signal, a demodulation circuit for a multilevel signal received on the vertical polarization and horizontal polarization sides and an equalization circuit for equalizing the output of the demodulation circuit And a cross polarization interference compensation circuit for inputting the outputs of the demodulation circuits on different polarization sides to obtain interference signals from different polarization sides, and an interference signal obtained by the cross polarization interference compensation circuit in reverse phase. An A / D conversion circuit that has an adder circuit that adds to the output of the equalization circuit, and further that, on the input side of the cross polarization interference compensation circuit, converts the outputs of the demodulation circuits on different polarization sides into digital signals, The demodulation circuit is supplied to the A / D conversion circuit An oscillator that outputs a clock signal that gives output sampling timing, a clock phase detection circuit that detects the phase of the clock signal from the output of the A / D conversion circuit, and outputs a control signal that controls the phase shift, and a clock phase detection It has a phase shift circuit that shifts the phase of the clock signal by a control signal output from the circuit to control sampling timing of the output of the demodulation circuit.

Further, the cross-polarization transmission receiver of digital multiplex radio according to claim 2 is the cross-polarization transmission receiver according to claim 1, wherein the clock phase detection circuit includes a polarity bit and an error signal corresponding to the output of the demodulation circuit. The signals are delayed from each other by one sampling timing and input from the A / D conversion circuit, and their exclusive OR is obtained.

According to a third aspect of the present invention, there is provided a digital multiplex radio cross polarization transmission receiver according to the second aspect, wherein the clock phase detection circuit delays a polarity bit corresponding to an output of the demodulation circuit by one sampling timing. A flip-flop circuit, an exclusive-OR circuit for inputting the polarity bit delayed by one sampling timing by the flip-flop circuit, the error signal, and obtaining an exclusive-OR of these are configured.

According to a fourth aspect of the present invention, there is provided a digital multiplex radio cross polarization transmission receiver according to the first aspect, wherein the A / D conversion circuit converts each of the I-channel and Q-channel multilevel signals into digital signals. It has an I-channel side A / D conversion circuit and a Q-channel side A / D conversion circuit for conversion, and the clock phase detection circuit includes an I-channel side A / D conversion circuit and a Q-side A / D conversion circuit.
It has first and second phase detection circuits for detecting the phase of the clock signal at each output of the channel side A / D conversion circuit, and further, the average value of the outputs of the first and second phase detection circuits It has the required circuit.

According to a fifth aspect of the present invention, there is provided a digital multiplex radio cross polarization transmission receiver according to the second aspect, wherein the clock phase detection circuit delays the polarity bit corresponding to the output of the demodulation circuit by one sampling timing. A first flip-flop circuit, a polarity bit delayed by one sampling timing by the first flip-flop circuit, and the first exclusive OR circuit for inputting the error signal and obtaining an exclusive OR of these; , A second flip-flop circuit for delaying the error signal by one sampling timing, an error signal delayed by one sampling timing by the second flip-flop circuit, and a polarity bit corresponding to the output of the demodulation circuit are input. The second exclusive-OR circuit for obtaining the exclusive-OR of Having a circuit for obtaining the mean value.

According to a sixth aspect of the present invention, there is provided a digital multi-radio cross polarization transmission receiver according to the fourth or fifth aspect, wherein the circuit for obtaining the average value is composed of a resistance addition circuit.

According to a seventh aspect of the present invention, there is provided a digital multiplex radio cross polarization transmission receiver according to the first aspect, wherein the phase shift circuit inputs the clock signal, and a signal of a predetermined fixed phase and a signal of a variable amplitude. And an amplitude control circuit for controlling the amplitude of the variable amplitude signal by the control signal,
It is configured to have a circuit for synthesizing a signal of a predetermined fixed phase and a signal whose amplitude is controlled by the amplitude control circuit.

According to an eighth aspect of the present invention, there is provided a digital multiplex radio cross polarization transmission receiver according to the seventh aspect, wherein the amplitude control circuit includes a pin diode, and a resistance value of the pin diode is changed according to the control signal. Configured to control.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar parts will be described with the same reference numerals or reference symbols.

FIG. 1 is a block diagram showing an embodiment of a cross polarization transmission receiver for digital multiplex radio according to the present invention. The basic configuration is the same as that of the conventional cross polarization transmission receiver of FIG.

The configuration of FIG. 8 different from the conventional one is that in FIG. 1, clock phase detection circuits 801, 811 and phase shift circuits 802, 812 are provided. As shown in FIG. 1, the demodulated baseband signal of the H polarization is converted into a digital signal by the A / D conversion circuits 901 and 902 in the cross polarization interference compensation circuit 20 on the V polarization side through the cable 40. It will be input later.

Further, the clock phase detector 801 produces an optimum phase control signal for the sampling clock in the A / D conversion circuit units 901 and 902 based on the digital data after A / D conversion. Then, based on this control signal, the clock phase adjustment circuit 802 shifts the phase of the recovered clock (CK1) from the oscillator 30 on the V polarization side to obtain the sample timing of the input analog signal of the cross polarization interference compensation circuit 20. Control. As a result, even if there is a variation in the delay of the cable that transmits the baseband signal, it is possible to bring out the maximum interference compensation function.

In FIG. 1, the demodulated V-polarized baseband signal is passed through the cable 41,
The A / D converter 9 is provided in the cross polarization interference compensation circuit 21 on the H polarization side.
It is input after being converted into a digital signal by 11, 912.

Further, the sampling phase of the A / D converters 911 and 912 is generated by the clock phase detector 811 based on the digital data after A / D conversion. Based on this control signal, the clock phase adjustment circuit 812 shifts the phase of the recovered clock (CK2) from the oscillator 31 on the V polarization side to control the sample timing of the input analog signal of the cross polarization interference compensation circuit 20. To do.

That is, the present invention solves the problem of the conventional device by adding a clock phase detection circuit and a clock phase adjustment circuit to the conventional configuration shown in FIG.

FIG. 2 shows clock phase detection circuits 801 and 8
It is a block diagram showing a first embodiment of No. 11. In the figure, since the circuit configuration is common, the configuration of the clock phase detection circuit 801 on the H polarization side is shown. That is, the flip-flop circuit 180 and the exclusive OR (EX-OR) circuit 181 are provided.

The polarity bit MSB which is the most significant weight bit from the A / D converter 901 and the error signal e are input. The polarity bit MSB is the flip-flop circuit 180.
Is delayed by one time slot by the EX-OR circuit 1
81 is input. These EX-OR logics are taken and output from the EX-OR circuit 181.

FIG. 5 shows such a clock phase detection circuit 80.
It is a figure explaining operation | movement of 1 and 811. FIG. 5 shows an eye pattern of a multilevel digital signal. A, A ', B,
B ′, C and C ′ are clock sampling timings, and AA ′, BB ′ and CC ′ are 1 respectively.
It is at a timing interval apart from the symbol.

Now, considering the data sampled at the timings A and A ', "1" and "0" are output with a probability of 50% in the control signal output according to the configuration of FIG. That is, since the error signal e of the data sampled at the timings A and A'is "0", the control signal output is a logical output according to the signal bits "1" and "0". Therefore, the probability of the control signal output being "1" or "0" is 50%.

On the other hand, considering the signals sampled at the timings of B and B ′, the error signals e at the timing of B and the signal bits at the timing of B ′ are EX-O.
R logic is taken.

Here, when the signal point passing through the uppermost portion at the timing of B is sampled, the frequency of "1" and "0" of the signal bit (MSB) sampled at B'is not 50%, At the same time, there is a correlation with the error signal e in the previous stage. Therefore, the frequency of the control signal, which is the output in the configuration of FIG. 2, is "1" or "0".

Here, the sampling timing is compared with the timing of A, and when the sampling timing is advanced (at the timing of B in FIG. 5), the output frequency of "0" is increased (see the timing of B ') and delayed. At this time (at the timing C, which is on the right side of the timing of A), the frequency of "1" increases (see the timing of C '). Therefore, it is possible to judge whether the sampling timing is advanced or delayed by the logic of the control signal.

FIG. 3 shows a second embodiment of the clock phase detection circuit. In the embodiment of FIG. 2, the input of the clock phase detection circuit 801 is the I / Q channel A / D.
In this example, the MSB and error signal from the converter 901 are used.

On the other hand, the configuration of FIG. 3 has the polarity bit M from the A / D converters 901 and 902 of the I and Q channels.
This is an example of using SB and the error signal e. In FIG. 3 as well, only the V polarization side A is shown because it has the same configuration.

In FIG. 3, circuits 280 and 281 can use the clock phase detection circuit shown in FIG. The control signals generated by the I and Q channels from the circuits 280 and 281 are averaged by the combined resistance circuit of the resistors R1 and R2. As a result, not only one channel but also the averaged control signals of both I and Q channels can be obtained.

FIG. 4 shows another embodiment of the clock phase detection circuit. The polarity signal MSB and the error signal e are respectively passed through the flip-flop circuits 180 and 280 to E.
Input to the X-OR circuits 181 and 281. Therefore, a more accurate control signal can be obtained by subtracting (inverting and adding) the two outputs from the EX-OR circuits 181, 281 having different delay delay relations.

That is, when the error signal e and the polarity signal MSB have the delay relationship described in FIG. 2, the sensitivity tends to be high when the timing of the sampling clock is early. In the opposite case (relationship between the flip-flop circuit 280 and the EX-OR circuit 281 in FIG. 4), the sensitivity becomes high when it is late. Therefore, by obtaining both control signals (outputs of the EX-OR circuits 181 and 281), uniform sensitivity can be obtained.

FIG. 6 shows an embodiment of the phase shift circuits 802 and 812, and FIG. 7 is an operation explanatory diagram thereof. Since they have the same configuration, they are shown as a phase shift circuit 802 on the V polarization side in the figure. This circuit uses the input clock C from the oscillator 30.
LK1 is a circuit that changes the phase according to the output control signal of the clock phase detection circuit 801 described above and outputs it.

The input clock CLK1 is converted into a sine wave by a low pass filter LPF. Then the DC component is removed and a constant offset is added,
The emitter and collector outputs of the transistor Tr output in-phase and anti-phase clocks with respect to the input clock CLK1.

On the other hand, in FIG. 6, the control signal is input to the operational amplifier 820 through the low pass filter. The bias voltage of the pin diode VD is controlled by the output of the operational amplifier 820.

In FIG. 7, is the in-phase output whose phase is fixedly shifted by the capacitance C ₁ connected to the emitter of the transistor Tr. Is an anti-phase output from the collector of the transistor Tr whose amplitude is changed by changing the resistance component of the pin diode VD by the output of the operational amplifier 820 corresponding to the magnitude of the control voltage.

By synthesizing the two sine waves at the synthesizing point CP, it is possible to obtain sine waves having different phases, as shown in FIG. The sine wave, 'is further converted into a rectangular wave by the comparator 821 to obtain the clock CLK01.

[0049]

As described above, according to the present invention, the sampling timing of the identification signal, which is the reference for error signal extraction in the cross polarization interference compensation circuit, is determined by the output result of the clock phase detection circuit. To control.
This makes it possible to maximize the interference compensation capability and improve the performance of the cross polarization interference compensation circuit. Further, there is provided a high performance digital multiplex radio cross polarization transmission receiver having a low error rate using the same.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital multi-radio cross polarization transmission receiver using a cross polarization compensation circuit of the present invention.

FIG. 2 is a first embodiment of the clock phase detection circuit of FIG.

FIG. 3 is a second embodiment of the clock phase detection circuit of FIG.

FIG. 4 is a third embodiment of the clock phase detection circuit of FIG.

FIG. 5 is a diagram illustrating an operation of a clock phase detection circuit.

FIG. 6 is a diagram showing an embodiment of the phase shift circuit of FIG.

FIG. 7 is a diagram illustrating an operation of a phase shift circuit.

FIG. 8 is a block diagram showing a configuration of a digital multiplex radio cross polarization transmission receiver using a conventional cross polarization compensation circuit.

[Explanation of symbols]

10, 11 Transversal equalizer 20, 21 Cross polarization interference compensation circuit 50, 51 Adder 60, 61 Demodulator 40, 41 Cable 30, 31 Oscillator 701, 702, 711, 712, 901, 902, 9
11, 912 A / D converter 801, 811 Clock phase detection circuit 802, 812 Phase shift circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Onyanagi 1-2-25, Ichibancho, Aoba-ku, Sendai City, Miyagi Prefecture Fujitsu Tohoku Digital Technology Co., Ltd.

Claims (8)

[Claims] 1. A digital multi-radio cross polarization transmission receiver for receiving multi-valued signals transmitted by vertical polarization and horizontal polarization orthogonal to each other, wherein the signals are received on the vertical polarization and horizontal polarization sides. Cross-polarization for inputting the demodulation circuit for the multilevel signal, the equalization circuit for equalizing the output of the demodulation circuit, and the output of the demodulation circuit on different polarization sides to obtain an interference signal from different polarization sides An interference compensating circuit, and an adder circuit for adding the interference signal obtained by the cross polarization interference compensating circuit to the output of the equalization circuit in antiphase, and further, on the input side of the cross polarization interference compensating circuit, A / which converts the outputs of the demodulation circuits on the different polarization sides into digital signals
A D conversion circuit, an oscillator that outputs a clock signal that is supplied to the A / D conversion circuit and gives sampling timing of the output of the demodulation circuit, and a phase of the clock signal is detected from the output of the A / D conversion circuit. A clock phase detection circuit that outputs a control signal that controls the phase shift, and a sampling timing of the output of the demodulation circuit that shifts the phase of the clock signal by the control signal output by the clock phase detection circuit. A cross-polarization transmission receiver of digital multiplex radio having a phase shift circuit for controlling the signal. 2. The clock phase detection circuit according to claim 1, wherein the polarity bit and the error signal corresponding to the output of the demodulation circuit are input from the A / D conversion circuit after being delayed by one sampling timing.
A cross-polarization transmission receiver of digital multiplex radio, characterized by obtaining an exclusive OR of these. 3. The flip-flop circuit for delaying the polarity bit corresponding to the output of the demodulation circuit by one sampling timing, and the clock phase detection circuit according to claim 2, being delayed by one sampling timing by the flip-flop circuit. And a polarity bit and the error signal are input, and an exclusive OR circuit for obtaining an exclusive OR of these signals is configured to be configured. 4. The A / D conversion circuit according to claim 1, wherein the A / D conversion circuit converts an I-channel multi-value signal and a Q-channel multi-value signal into digital signals, and a Q-channel side A / D conversion circuit. A D-conversion circuit, wherein the clock phase detection circuit detects the phase of the clock signal at each output of the I-channel side A / D conversion circuit and the Q-channel side A / D conversion circuit; And a circuit for obtaining an average value of the outputs of the first and second phase detection circuits. 5. The clock phase detection circuit according to claim 2, further comprising a first flip-flop circuit that delays a polarity bit corresponding to an output of the demodulation circuit by one sampling timing, and the first flip-flop circuit. A polarity bit delayed by one sampling timing, a first exclusive OR circuit for inputting the error signal and obtaining an exclusive OR of these signals, and a second flip-flop for delaying the error signal by one sampling timing. Circuit and a second exclusive gate for inputting the error signal delayed by one sampling timing by the second flip-flop circuit and the polarity bit corresponding to the output of the demodulation circuit, and obtaining the exclusive OR of these. A logical OR circuit and a circuit for obtaining an average value of outputs of the first and second exclusive OR circuits. Digital multiplex radio cross-polarized transmission receiver that. 6. The cross polarization transmission receiver of digital multiplex radio according to claim 4, wherein the circuit for obtaining the average value is constituted by a resistance addition circuit. 7. The circuit according to claim 1, wherein the phase shift circuit receives the clock signal and outputs a signal of a predetermined fixed phase and a signal of variable amplitude, and the amplitude of the signal of variable amplitude. A digital multiplex radio characterized by comprising an amplitude control circuit controlled by a control signal, and a circuit for synthesizing the signal of the predetermined fixed phase and the signal of which the amplitude is controlled by the amplitude control circuit. Cross polarization transmission receiver. 8. The digital multiplex radio according to claim 7, wherein the amplitude control circuit includes a pin diode, and is configured to variably control a resistance value of the pin diode according to the control signal. Cross polarization transmission receiver.