JPH0955771A - Digitally sent signal demodulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an error in demodulation control and prevent reception performance from deteriorating by selecting an error signal corresponding to a main signal having its error corrected and supplying it to a circuit part which performs demodulation control through a signal selection part. SOLUTION: A selector 42 as the signal selection part is supplied with a main signal and an error signal of an I channel and a Q channel outputted by an EQL(equalizer) 38 and also supplied with a main signal and an error signal of the I channel and Q channel after error correction which are outputted by a decoder 40. Then the selector 42 selects and outputs the main signal and error signal of the I channel and Q channel outputted by the EQL 38 at the time of synchronism acquiring operation with a switching control signal supplied from a host device through a terminal 42a and the main signal and error signal of the I channel and Q channel after error correction which are outputted by the decoder 40 after the synchronism acquiring operation ends.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission signal demodulation system, and more particularly to a system for demodulating and outputting a digital transmission signal. In a digital transmission system having a long relay interval and a small reception power, an error correction code is used to reduce the signal power to noise power (C / N ratio) in order to obtain a predetermined line code error rate.

As an error correction method, for example, convolutional coding / Viterbi decoding is used. With the Viterbi decoding, soft-decision decoding can be realized relatively easily.

[0003]

2. Description of the Related Art FIG. 6 shows a block diagram of an example of a conventional system. In the figure, a digital transmission signal of a predetermined frequency received by the antenna 10 is converted into an intermediate frequency signal by the receiving circuit 11. This intermediate frequency signal is supplied to the hybrid 12 and separated into an I channel and a Q channel. The signals of the I channel and the Q channel are mixed by the mixers 13A and 13A.
The reproduction carriers from the VCO (Voltage Controlled Oscillator) 14 are mixed by each B and demodulated, and then the A / D converter 1
For example, 6-bit reproduction data is formed in each of 5A and 15B. In the 6-bit reproduction data for each of the I channel and Q channel, the upper 3 bits are the main signal and the lower 3 bits are the error signal.

The reproduced data of the I channel and the Q channel are demodulated by the AGC (automatic gain control) circuit 16, the ADC (automatic drift control) circuit 17, and the EQL (equalizer) 18, respectively. , To the decoder 20. The decoder 20 performs, for example, Viterbi decoding, performs error correction, obtains 3-bit decoded data for each of the I channel and the Q channel, and outputs the decoded data from the terminals 21a and 21b.

Further, the integrator 23 integrates the error signals of the I channel and Q channel of the EQL 18 output to obtain V
The phase control signal supplied to the CO 14 is generated. Integrator 2
Reference numeral 4 integrates the I channel and Q channel main signals and the error signal output from the EQL 18 to generate a gain control signal to be supplied to the AGC circuit 16. The integrator 25 integrates the I channel and Q channel error signals output from the EQL 18 to generate a drift control signal to be supplied to the ADC circuit 17. The integrator 26 integrates the I channel and Q channel main signals and the error signal of the EQL 18 output to integrate the EQL 18
The coefficient value of the transversal filter that composes is generated and supplied to the EQL 18.

[0006]

In the demodulation control of the received signal, a control signal is generated in each of the integrators 23 to 26 based on the main signals of the I and Q channels output by the EQL 18 and the error signal. Phase control, gain control, drift control of regenerated carrier using control signal,
Each equalization control is performed.

The error signal output from the EQL 18 is shown in FIG.
As shown in (A), the I channel component at the reception signal point position X is 1.75 and the Q channel component is 1.75,
When there is a signal point A (1,1) and a signal point B (1,3), the Euclidean distance (straight line distance in the figure) from the received signal point position X (1.75, 1.75) is the most. Near signal point A
Using (1,1) as the main signal, the received signal point position X (1.7
5, 1.75) and the signal point A (1,1) difference E _I = +,
The error signals are 0.75 and E _Q = + 0.75.

Therefore, if error correction is performed in the decoder 20 and the main signal at the received signal point position X is the signal point B (1,3) as shown in FIG. E _I
= + 0.75, and E _Q = -1.25. That is, if there is an error, it means that the demodulation control of the received signal is erroneous, and the erroneous demodulation control may deteriorate the reception performance.

The present invention has been made in view of the above points,
An object of the present invention is to provide a digital transmission signal demodulation system capable of preventing erroneous demodulation control when a digital transmission signal has an error and preventing deterioration of reception performance.

[0010]

According to a first aspect of the present invention, a digital transmission signal encoded by an error correction code and digitally modulated is subjected to demodulation control based on a main signal of demodulation data and an error signal to perform digital control. In a digital transmission signal demodulation system that demodulates and outputs an error-corrected main signal by decoding using the obtained main signal and error signal of the demodulated data, the main signal and error signal of the error-corrected main signal and demodulated data Error signal correction section for obtaining an error signal for the error-corrected main signal from, the main signal and error signal of the demodulated data, and the error-corrected main signal and the error signal for the error signal are selected to perform demodulation control. And a signal selection unit that supplies the circuit unit to perform.

Therefore, the main signal error-corrected by the signal selection unit and the error signal corresponding to the main signal are selected and supplied to the circuit unit which performs demodulation control, whereby the demodulation control is prevented from becoming erroneous, and deterioration of the reception performance is prevented. it can. In the invention described in claim 2, the error correction code is multilevel coding modulation.

Therefore, strong error correction can be performed. According to the third aspect of the present invention, the circuit unit that performs the demodulation control is at least one of automatic gain control, automatic drift control, equalization, and carrier reproduction. Therefore, automatic gain control, automatic drift control, equalization, and carrier reproduction can be performed without error.

In the invention according to claim 4, the signal selecting section selects the main signal and the error signal of the demodulated data at the time of the synchronization pull-in, and selects the main signal and the error signal corresponding to the error-corrected main signal after the synchronization pull-in. For this reason, it is possible to prevent delay in demodulation control during synchronization pull-in, and it is possible to perform error-free demodulation control after synchronization pull-in.

[0014]

1 shows a block diagram of an embodiment of the system of the present invention. In the figure, the digital transmission signal of a predetermined frequency received by the antenna 30 is converted into an intermediate frequency signal by the receiving circuit 31. This intermediate frequency signal is supplied to the hybrid 32 and separated into an I channel and a Q channel. The signals of the I channel and the Q channel are supplied to the VCO (voltage controlled oscillator) 34 by the mixers 33A and 33B, respectively.
After reproducing carrier is mixed and demodulated, A / D
For example, 6-bit reproduction data is produced by each of the converters 35A and 35B. In the 6-bit reproduction data for each of the I channel and Q channel, the upper 3 bits are the main signal and the lower 3 bits are the error signal.

The reproduced data of each of the I channel and the Q channel is subjected to demodulation control by an AGC (automatic gain control) circuit 36, an ADC (automatic drift control) circuit 37, and an EQL (equalizer) 38. , To the decoder 40. The decoder 40 performs error correction, for example, by decoding MLCM (Multi Level Coating Modulation). If there is an error by this, the main signals of the I channel and the Q channel for which the error is corrected are input to the terminals 41a, 4a.
1b and supplies the main signal and the error signal to the selector 42. Further, the decoder 40 generates an alarm signal when the error rate exceeds a predetermined threshold and outputs the alarm signal to the terminal 41.
Output from c.

The selector 42, which is a signal selection unit, has an EQ
The main signals and error signals of the I and Q channels output from L38 are supplied, and the main signals and error signals of the I and Q channels after error correction output from the decoder 40 are supplied. The selector 42 selects the main signal and the error signal of the I channel and Q channel output from the EQL 38 at the time of the synchronous pull-in operation by the switching control signal supplied from the higher-order device through the terminal 42a, and after the synchronous pull-in operation is completed. The error-corrected main signals and error signals of the I and Q channels output from the decoder 40 are selected and output.

The integrator 43 integrates the error signals of the I channel and the Q channel to generate a phase control signal to be supplied to the VCO 34. The integrator 44 is the selector 42
The output I-channel and Q-channel main signals and the error signal are integrated to generate a gain control signal to be supplied to the AGC circuit 36. The integrator 45 integrates the I-channel and Q-channel error signals output from the selector 42 to generate a drift control signal to be supplied to the ADC circuit 37. Integrator 4
A reference numeral 6 integrates the I-channel and Q-channel main signals output from the selector 42 and the error signal to generate a coefficient value of a transversal filter which constitutes the EQL 38 to generate EQL3.
Supply to 8.

FIG. 2 shows a block diagram of the decoder 40. In the figure, a main signal and an error signal (accounting 12 bits) of each of the I channel and the Q channel are input to the terminal 50 from the EQL 38 and are supplied to the frame synchronization circuit 51 and the phase indetermination removal circuit 52. The frame synchronization circuit 51 compares the supplied main signals of the I and Q channels with a frame synchronization pattern of four states in which the phase is rotated by 90 degrees, detects which phase rotation state the frame synchronization bit of the main signal is, and detects the phase. It is supplied to the uncertainty removal circuit 52.

As shown in FIG. 3, the main signal of the I channel and Q channel has a superframe of 3564 bits composed of first and second subframes, and the first 36 bits of each subframe are specified. It is used as a frame synchronization bit of a bit pattern. Further, in the case of QAM demodulation, since the phase is in one of four states rotated by 90 degrees, it is necessary to set the phase to 0 degree.

The phase uncertain removal circuit 52 rotates the phase of the main signal based on the phase rotation state detection signal so that the phase becomes zero.
Then, the main signals of the I and Q channels and the error signal are supplied to the Viterbi decoding circuit 53 for decoding the MLCM.

FIG. 4 is a block diagram of the Viterbi decoding circuit 53. In the figure, a main signal and an error signal of the I channel and the Q channel are input to the terminal 61 and are supplied to the delay circuit 62 and the branch metric calculation unit 63. The branch metric calculation unit 63 performs the level 1 branch metric calculation and supplies the calculation result (branch metric value of each branch) to the ACS unit 64. The ACS unit 64 adds, compares, and selects paths for all branch metric values to perform level 1 decoding and correction. The calculation result is supplied to the delay circuit 65. In addition, the re-encoding unit 6
6 again encodes the calculation result of the ACS unit 64 and supplies it to the second level branch metric calculation unit 67.

The branch metric calculation unit 67 is a delay unit 6
The re-encoding unit 66 output is added to the main signal and the error signal of the I channel and the Q channel, which are synchronized in 2, and the branch metric calculation of the level 2 is performed, and the calculation result is ACS.
Supply to the section 68. The ACS unit 68 performs level 2 decoding and correction based on this.

The calculation result of the ACS unit 68 is the delay circuit 6
9. Re-encoding unit 66 output synchronized with 9 and delay circuit 7
It is supplied to the signal point determination unit 71 together with the main signals of the I channel and the Q channel and the error signal which are synchronized with 0,
Here, the signal points represented by the main signals of the I and Q channels are determined. The delay circuit 65 is added to the upper bits of the main signals of the I and Q channels obtained by this.
The output of the ACS section 64 that has passed through is combined as a lower bit and output from the terminal 73 as an I-channel and Q-channel main signal for which error correction has been performed.
4 is supplied.

On the other hand, the demapping unit 75 demaps the I-channel and Q-channel main signals of the output of the delay unit 70, which are not error-corrected, and supplies them to the comparison unit 74.
The comparison unit 74 calculates the number of correction bits from the error-corrected main signal and the error-uncorrected main signal and outputs it from the terminal 76.

Referring back to FIG. 2, the main signals and error signals of the I channel and Q channel before being supplied to the Viterbi decoding circuit 53, and the I channel and Q channel decoded and error-corrected by the Viterbi decoding circuit 53. And the main signal of are supplied to the error signal correction unit 54.

The error signal correction unit 54 decodes the I channel after decoding when the main signals of the I channel and Q channel before decoding indicate the signal point A shown in FIG. 5 and the error signals are E _I and E _Q. If the main signal of the Q channel is corrected to the signal point B, the error signals of the I channel and the Q channel after decoding are corrected to E _I = E _I , E _Q = E _Q -2.
Similarly, if corrected to signal point C, E _I = E _I −2, E
Corrected as _Q = E _Q -2, and if corrected to signal point D, E
Corrected as _I = E _I −2, E _Q = E _Q, and if corrected to the signal point E, corrected as E _I = E _I −2, E _Q = E _Q +2,
If corrected to the signal point F, E _I = E _I , E _Q = E _Q +
Corrected to 2, and if corrected to the signal point G, E _I = E _I +
2, E _Q = E _Q +2 is corrected, and if corrected to the signal point H, E _I = E _I + 2, E _Q = E _Q is corrected, and if corrected to the signal point I, E _I = E Correct it as _I +2, _EQ = _EQ -2. The error signal correction unit 54 outputs the I-channel and Q-channel error signals thus corrected together with the decoded and corrected I-channel and Q-channel main signals from the terminal 56.

Further, the number of correction bits output from the Viterbi decoding circuit 53 is supplied to the error counter 55, and the error counter 55 counts the number of correction bits supplied at regular time intervals and counts up when a predetermined threshold value is exceeded. An alarm signal is output from the terminal 57. In this way, by selecting the main signal error-corrected by the selector 42 and the error signal corresponding to the main signal and supplying the selected main signal to the circuit section that performs demodulation control, the demodulation control is prevented from becoming erroneous, and deterioration of the reception performance can be prevented.
Further, since error correction is performed by MLCM, cooperative error correction is possible, and automatic gain control, automatic drift control,
Equalization and carrier reproduction can be performed without error.

Further, since decoding requires a little time, the main signal and the error signal of the demodulated data are selected at the time of the synchronization pull-in, and the main signal error-corrected after the synchronization pull-in and the error signal corresponding thereto are selected. It is possible to prevent delay in demodulation control during synchronization pull-in, and it is possible to perform error-free demodulation control after synchronization pull-in.

[0029]

As described above, the invention according to claim 1 is
Digitally demodulates a digital transmission signal encoded by an error correction code and digitally modulated based on the main signal and error signal of the demodulated data, and demodulates digitally, and decodes using the main signal and error signal of the obtained demodulated data In the digital transmission signal demodulation system for converting the error-corrected main signal and outputting the error-corrected main signal, an error signal correction unit for obtaining an error signal for the error-corrected main signal from the error-corrected main signal and the main signal and error signal of demodulated data, It has a signal selection unit that selects one of a main signal and error signal of demodulated data and an error-corrected main signal and an error signal corresponding thereto and supplies the selected signal to a circuit unit that performs demodulation control.

Therefore, the main signal error-corrected by the signal selection unit and the error signal corresponding to the main signal are selected and supplied to the circuit unit which performs demodulation control, whereby the demodulation control is prevented from becoming erroneous, and deterioration of the reception performance is prevented. it can. In the invention described in claim 2, the error correction code is multilevel coding modulation.

Therefore, strong error correction can be performed. According to the third aspect of the present invention, the circuit unit that performs the demodulation control is at least one of automatic gain control, automatic drift control, equalization, and carrier reproduction. Therefore, automatic gain control, automatic drift control, equalization, and carrier reproduction can be performed without error.

According to the invention described in claim 4, the signal selecting section selects the main signal and the error signal of the demodulated data at the time of the synchronization pull-in, and selects the main signal which is error-corrected after the synchronization pull-in and the error signal corresponding thereto. Therefore, it is possible to prevent delay in the demodulation control at the time of synchronization pull-in, and to perform error-free demodulation control after the synchronization pull-in, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of the system of the present invention.

FIG. 2 is a block diagram of a decoder.

FIG. 3 is a diagram showing a signal format.

FIG. 4 is a block diagram of a Viterbi decoding circuit.

FIG. 5 is a diagram for explaining error signal correction.

FIG. 6 is a block diagram of a conventional system.

FIG. 7 is a diagram for explaining a change in an error signal due to error correction.

[Explanation of symbols]

 33A, 33B Mixer 34 VCO 35A, 35B A / D Converter 36 AGC Circuit 37 ADC Circuit 38 Equalizer 40 Decoder 42 Selector 53 Viterbi Decoder 54 Error Signal Corrector 55 Error Counter

Front page continued (72) Inventor Noboru Suzuki No. 2-25 Ichibancho, Aoba-ku, Sendai-shi, Miyagi Prefecture Fujitsu Tohoku Digital Technology Co., Ltd. (72) Inventor Yoshihiko Taki Ichibancho, Aoba-ku, Sendai-shi, Miyagi Prefecture 1-225 Fujitsu Tohoku Digital Technology Co., Ltd. (72) Inventor Toru Sasaki 1-2-25 Ichibancho, Aoba-ku, Sendai City, Miyagi Fujitsu Tohoku Digital Technology Co., Ltd.

Claims (4)

[Claims] 1. A main signal and an error of the demodulated data obtained by digitally demodulating a digital transmission signal encoded by an error correction code and digitally modulated based on the main signal and the error signal of the demodulated data. In a digital transmission signal demodulation system for decoding a signal and outputting an error-corrected main signal, an error for obtaining an error signal for the error-corrected main signal from the error-corrected main signal and the demodulated data main signal and error signal A signal correction unit, and a signal selection unit that selects one of a main signal and error signal of demodulated data, an error-corrected main signal, and an error signal corresponding to the main signal and supplies the signal to a circuit unit that performs demodulation control. A digital transmission signal demodulation system characterized by. 2. The digital transmission signal demodulation system according to claim 1, wherein the error correction code is a multi-level coding modulation. 3. The circuit unit for performing the demodulation control is at least one of automatic gain control, automatic drift control, equalization, and carrier reproduction.
The digital transmission signal demodulation system described. 4. The signal selecting unit selects a main signal and an error signal of demodulated data at the time of synchronization pull-in, and selects a main signal and an error signal corresponding to the main signal that have been error-corrected after the synchronization pull-in. The digital transmission signal demodulation system described.