JPS55139696A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS55139696A
JPS55139696A JP4468579A JP4468579A JPS55139696A JP S55139696 A JPS55139696 A JP S55139696A JP 4468579 A JP4468579 A JP 4468579A JP 4468579 A JP4468579 A JP 4468579A JP S55139696 A JPS55139696 A JP S55139696A
Authority
JP
Japan
Prior art keywords
input signal
circuit
memories
address
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4468579A
Other languages
Japanese (ja)
Other versions
JPS594800B2 (en
Inventor
Haruo Tsuda
Takayuki Okino
Toshio Iyota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54044685A priority Critical patent/JPS594800B2/en
Publication of JPS55139696A publication Critical patent/JPS55139696A/en
Publication of JPS594800B2 publication Critical patent/JPS594800B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To control the writing of an input signal, including an error, in a memory with simple constitution by generating any other address than addresses assigned to respective memories from an address generating circuit according to the abnormality of the input signal.
CONSTITUTION: For every frame clock separated from an input signal by frame synchronizing circuit 1, address generating circuit 22 generates addresses corresponding to alternate memories 6 and 7 and address gates 3 and 5 are opened alternately to write the input signal in memories 6 and 7. Those memory contents are alternately read out when no write comes into effect through 1/2 dividing circuit 2 dividing frame clocks of circuit 1 by two and selecting circuit 21. Once input abnormality detecting circuit 23 detects the input signal being abnormal, circuit 22 generates any other address than address assigned to memories 6 and 7 and while gates 3 and 5 stay closed, the writing of the incorrect input signal in memories 6 and 7 is controlled with the simple constitution; and the correct input signal right before writing is read out from memories 6 and 7 and the following signal processing is easy and simple.
COPYRIGHT: (C)1980,JPO&Japio
JP54044685A 1979-04-12 1979-04-12 memory circuit Expired JPS594800B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54044685A JPS594800B2 (en) 1979-04-12 1979-04-12 memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54044685A JPS594800B2 (en) 1979-04-12 1979-04-12 memory circuit

Publications (2)

Publication Number Publication Date
JPS55139696A true JPS55139696A (en) 1980-10-31
JPS594800B2 JPS594800B2 (en) 1984-01-31

Family

ID=12698277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54044685A Expired JPS594800B2 (en) 1979-04-12 1979-04-12 memory circuit

Country Status (1)

Country Link
JP (1) JPS594800B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0712127U (en) * 1993-07-30 1995-02-28 オリオン電機株式会社 Examination table

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0712127U (en) * 1993-07-30 1995-02-28 オリオン電機株式会社 Examination table

Also Published As

Publication number Publication date
JPS594800B2 (en) 1984-01-31

Similar Documents

Publication Publication Date Title
JPS55139696A (en) Memory circuit
JPS55134442A (en) Data transfer unit
JPS5447438A (en) Control system for scratch memory
JPS5318925A (en) Memory control unit
JPS5443630A (en) Memory access control system
JPS522330A (en) Data processig unit
JPS5549073A (en) Memory unit
JPS57113497A (en) Error correction system
JPS563485A (en) Buffer memory device
JPS5634194A (en) Memory unit
JPS57193847A (en) Memory bank dividing circuit
JPS5687153A (en) Controller for auxiliary memory
JPS5576446A (en) Pre-fetch control system
JPS5654696A (en) Memory device
JPS5563420A (en) Detector for data train
JPS55134443A (en) Data processing unit
JPS5599652A (en) Microprogram control unit
JPS5699545A (en) Microprogram control electronic computer
JPS57135496A (en) P-rom compensating circuit
JPS5693191A (en) Memory error correction and automatic diagnosis system
JPS533746A (en) Memory control system
JPS5533249A (en) Microprogram controller
JPS6474644A (en) Data processor for memory
JPS5591045A (en) Time-division information process system
JPS5650450A (en) Memory control system