JPS594800B2 - memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a circuit type which is equipped with a plurality of memories, which inputs and outputs an input signal on a frame-by-frame basis, and which is capable of reducing the passage of errors.

This invention relates to the invention of the formula. Memory circuits that store signals received from a transmission path in units of frames and output them in units of frames have already been widely used.

FIG. 1 is a block diagram showing the configuration of such a conventional memory circuit.

In the figure, an input signal a5 is separated from a frame clock in a frame synchronization circuit 1. The frame clock signal is frequency-divided by 2 in a 1/2 frequency divider circuit 2. The frequency-divided signal is passed through AND gate 3 and inverter 4 to AN
D gate 5 and AND gates 3 and 5 are added to 10
Open alternately.

As a result, alternate input signals are applied to the memories 6 and T for each frame and are stored therein. The outputs of the memories 6 and T are input to an OR gate 10 via AND gates 8 and 9, respectively. The AND gates 8 and 9 are connected to the output of the 1/2 frequency divider 152 and the output power of the inverter 4, respectively.
9 is alternately opened and closed, and the output of memory 6 and T is OR gate 1.
0 and is alternately output to produce an output b. In this manner, in the circuit of FIG. 1, one memory 6 and one memory OT are selected alternately to write and store an input signal, and at the same time, the contents are read from the memory on the side that is not used for writing.

This operation is repeated once every frame.
AND gates 8, 9 and OR gate 10 are selection circuit 1
1■5 is formed. In the circuit shown in FIG. 1, the output b & balance is provided with a parity check circuit 12, for example, which checks the parity error in the output 1 for each frame, thereby checking the signal of that frame. It is used as information after determining whether it is valid and -30.

However, the parity check alone has low error detection ability, and therefore there may be cases where an erroneous signal is passed.

Further, when processing information, it is necessary to determine whether the signal of the frame is valid or not in step 15, and then process the signal. Note that the most common cause of such errors is usually a momentary interruption in the transmission line. The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to add an input signal inhibiting function to the memory circuit when an error occurs, in addition to parity checking, and to suppress the signal of a frame containing an error. One object of the present invention is to provide a memory circuit that can simplify processing in an information processing section by not allowing the information to pass through.

In order to achieve this object, the memory circuit 1 of the present invention includes a plurality of memories and writes and reads an input signal one by one in the plurality of memories alternately one by one at regular intervals. An address generation circuit that generates an address for selecting a memory into which a signal is to be written; and an input error generation circuit that detects that an input signal is abnormal and generates a signal, 1, the address generation circuit generates addresses other than those assigned to the plurality of memories (this is characterized in that writing of input signals containing errors to the memory is suppressed). Examples will be described below.

FIG. 2 is a block diagram showing the configuration of one embodiment of the memory circuit of the present invention.

In FIG. 1, symbols 1, 2, 3, 5, 6, 7 and A,
The situation in b is the same as in Figure 1. 21
is a selection circuit (SEL), 22 is an address generation circuit, 23
24 is an input abnormality detection circuit and a decoder.

In FIG. 2 f, the frame synchronization circuit 1 separates the frame 1 and clock from the input signal a, and then supplies the address generation circuit 222 with the frame synchronization circuit 1.
I'll give you this.

The address generation circuit 22 thereby alternately generates an address A for the memory 6 and an address B for the memory 7 every frame. Decoder 23 has address A
. On the other hand, the frame clock signal 1/2 separated by the frame synchronization circuit 1 is written into the memories 6 and 7.
It is added to the frequency divider circuit 2 and divided by two. The frequency-divided signal is applied to the selection circuit 21.

The selection circuit 21, in synchronization with the address generation circuit 22, alternately selects signals read out one frame at a time from the memories 6 and 7 that are not in the write state and outputs them as output b. When an abnormality such as a disconnection occurs in the input signal a, the input abnormality detection circuit 23 detects this and generates a signal. The address generation circuit 22 generates an address other than the above-mentioned addresses A and B, for example C, in response to the signal 1 from the input abnormality detection circuit 23. When decoder 24 receives address C, it does not output "1" to either AND gates 3 and 5. Therefore, gates 3 and 5 are both closed, input signal a is inhibited, and no new writing is performed in either memory 6 or 7. In this state, the memories 6 and 7 store the input signal before the occurrence of the input signal abnormality, so by reading this through the selection circuit 21, 1. It can be output.

The memory circuit of the present invention can be used when receiving alarm signals from various devices having one input source in a remote location. This is suitable for use in a device that can simplify subsequent processing by outputting an input signal from one frame before, rather than passing an erroneous signal through one output.

In such devices, the input signal usually changes slowly, so outputting the input signal one frame before often does not cause any major problems.

Therefore, when the memory circuit of the present invention is used, it is possible to prevent disturbances caused by outputting erroneous signals based on abnormalities in human input signals, simplify subsequent processing, and thus simplify the device as a whole. It is possible and extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional memory circuit, and FIG. 2 is a block diagram showing the configuration of an embodiment of the memory circuit of the present invention. 1...Frame synchronization circuit, 2...1/
2 frequency divider circuit, 3...AND gate, 4...
...Inverter, 5...AND gate, 6,7
...Memory, 8,9...AND gate, 10...0R gate, 11...
Selection circuit, 12... Parity check circuit, 2
1... Selection circuit (SEL), 22...
Address generation circuit, 23... Input abnormality detection circuit, 24... Decoder.

Claims (1)

[Claims] 1. In a memory circuit that includes a plurality of memories and that sequentially writes and reads input signals to and from the plurality of memories at regular intervals, an address generation circuit that generates an address for selecting a memory to which the input signal is to be written; , an input abnormality generating circuit that detects that an input signal is abnormal and generates a signal, and a signal other than that allocated to the plurality of memories from the address generating circuit according to the signal of the input abnormality generating circuit. A memory circuit characterized in that writing of an input signal containing an error to a memory is suppressed by generating an address.