JPS6052993A - Memory address control device - Google Patents

Abstract

PURPOSE:To simplify the constitution of an address monitor device by processing logically an output for detecting whether the range of one address and the other address are correct or not, and controlling a load to an address counter. CONSTITUTION:The time base of a reproducing signal is corrected by write at each frame address to a memory, and the read-out of a diagonal direction having no interference. Basing on the output of an address detector 30 for detecting an open looped read-out address 4a and a check clock Sa, on OR gate 36 generates a clock in case a read-out frame address is 3 and a word address is 0. In this case, when a write frame address becomes other than 0-2, an address area detector 31 outputs 0 to detect an address abnormality, the output of the gate 36 is outputted as a load clock 6a through the Or gate 37, a load value 6b is applied and written to a write use fram address counter, and the frame address is corrected so that write and read-out address lines do not cross each other. In this way, a comparator, a subtractor, etc. become unnecessary to simplify the constitution of an address monitor device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a memory address control device, and particularly to a memory address 11 and an IJ wrapping U having a more simplified circuit configuration.

[Description of the Prior Art] In digital audio discs and PCM recorders, in order to eliminate rotational unevenness in the rotation system (hereinafter referred to as "jitter") during playback, playback data is written to memory using a clock that follows jitter, for example, using a crystal A commonly used method is to read data from memory using a clock generated from an oscillator. In this way, the memory address control i &
As an example of an Il device, there has conventionally been one having the configuration shown in FIG.

In FIG. 7, 2.4, 8.10 are counters, and counters 2 and 4 are the first counters that generate read addresses.
A memory address generation circuit (successive address generation circuit) is configured. Further, counters 8 and 10 constitute a second address generation circuit (write address generation circuit) that generates a write address. Terminals 1, 3, 5.7, and 9.13 are input terminals, and terminal 12 is an output terminal.

The counter 2 is a counter that generates a read address corresponding to each word in one frame, and the read word clock (hereinafter referred to as rRWcKJ) Ia is input from the input terminal 1, and the read word clock (hereinafter referred to as rRWcKJ) Ia is input to one input (6 inputs) of the selector 11. give the output. The counter 4 is a counter that updates its count value every frame during reading, and receives a read frame clock (hereinafter referred to as rRFCKJ) 3 a from an input terminal 3 . The output 4a of the counter 4 is applied to six inputs of the safety lid 11 and the address monitoring bag @6.

The counter 8 is a counter that generates an address corresponding to each word in one frame at the time of writing, and a write word clock (rWWcKJ>78, hereinafter referred to as rWWcKJ) is input from the input terminal 7, and its output is sent to the selector 11. The counter 10 is a counter that updates its count value every frame during writing, and receives a write frame clock (hereinafter "W") from the input terminal 9.
FCKJ) 9a is input. The output 10a of the counter 10 is applied to the B input of the selector 11 and the address monitoring bag u6.

As described above, the address monitoring device 6 uses the respective frame addresses of the write system and the read system (given from the counters 4 and 10) and the check clock 5a input from the input terminal 5 to It is determined whether the relationship between the write-related frame address and the read-related frame address is normal or abnormal. If the address relationship between both systems becomes abnormal, the address monitoring device 6 loads the value 6b calculated by the address monitoring device 6 into the counter 10 at the timing of the load clock 6a. The selector 11 inputs the write address and subsequent address given from the counters 2 and 4.8° 10, respectively, to the input terminal 1.
Switching by the select signal 13a given from 3,
Output to output terminal 12. The output signal is supplied from the output terminal 12 to a memory (not shown).

Next, the conventional memory address 1lillt shown in FIG.
The detailed operation of the II device will be explained with reference to FIGS. 2 to 4.

Figure 2 shows the writing system time chart.
9a shows the structure of one frame of the input signal including the synchronization signal (SYNC) and four data DO-D3, and 9a is W F
CK, and 7a indicates WWCK.

FIG. 3 shows a read-out system time chart, B shows the structure of read data for one frame, and 3a shows the RFC
1a indicates RWCK, and 5a indicates the timing of the check clock.

FIG. 4 shows a 64-bit memory map as an example, where the horizontal axis specifies the address given by counter 2 or counter 8 corresponding to DO-D3, and the vertical axis specifies the address given by counter 4 or counter 10. The frame address to be given is defined. In FIG. 4, the frame addresses are divided into 0 to 15, and counter 4 and counter 10 sequentially cycle through the count values of 0 to 15. Note that the △ mark in the figure indicates write data, and the ◯ mark indicates read data. A write line and a read line that respectively connect each write data and each read data indicate the write power and read output of data to the memory.

The writing power and subsequent output of such data to the memory, in other words, how the writing lines and reading lines are defined differs depending on the signal processing of each device. In this embodiment, it is assumed that the writing power and reading power are as shown in FIG. 4, for example.

Referring to FIGS. 1 to 4, at time [1, when W F CK 9 a is applied from input terminal 9, counter 8 is reset, and counter 10 has its count value updated by 1. , its value becomes "1". Next, at time t2, Do of the reproduced signal of A (Figure 2) is (
1, 0) [X in (X, V) indicates the frame address of the memory map (FIG. 4), y indicates the word address] and updates the count value of the counter 8 by 1.

This operation is performed sequentially, and at time t3, (1, 3) is written to D3 of the reproduced signal, and data writing for one frame is completed. Then, writing of the next frame is performed at frame address 2.

On the other hand, for reading, at time t4, the counter 2 is reset by the RFCK 3a, and the count 1 of the counter 4 is updated by 1, giving the address (3, 0) to the memory. At time t5, the data at address (3, 0>) is read and at the same time the count value of counter 2 is set to 1.
The count value of the counter 4 is updated by 4, and an address (7°1) is generated. At time t6, reading of data at address (15°3) is completed, and reading of data for one frame is completed.

The above writing and reading are performed in a time division manner by the selector 11, and one frame is written.

When the read cycle is the same, the lines of the write system and the continuous output system (see FIG. 4) do not intersect, and the relationship shown in FIG. 4 is maintained.

However, the reproduced signals A and W, , I-CK 9 a
, WWCK7a usually contains jitter, and this jitter may cause the write line and read line to intersect. To prevent this crossing of both lines, generally avoid frame addresses above and below the write line,
I'm trying to set up a series of lines. In the case of FIG. 4, frame addresses O and 2 serve as jitter margins, and a margin of ±1 frame is provided.

However, if the jitter is within the margin set above, there is no problem; however, if the jitter exceeds the margin, or due to disturbances, the write line and read line may intersect. In this state, it goes without saying that correct data reproduction is impossible.

Therefore, in order to prevent this, an Atonenos supervisory device 6 shown in FIG. 1 is provided. The address monitoring device 6 detects the intersection of both lines and loads the value 6b calculated by the monitoring device 6 into the counter 10 at timing 6a. As a result, the values of the counter 10 are returned to their normal states, and the intersection between the write line and the read line is corrected.

FIG. 5 is a block diagram of a conventional circuit of this address monitoring device 6. The conventional address monitoring device 6 includes an address area detector 20, a comparator 21, and an OR gate 24.
, 26, and a subtractor 29. In FIG. 4, when looking at the column of word address O, it is found that in word addresses 3 to 15, successive addresses have larger values than write addresses. Therefore, in the address area detector 20 shown in FIG. 5, the output 4a of the counter 4 which is the read frame address is input, and the frame address
5, O is output to one input of the OR gate 26. The check clock 5a is input to the other input of the OR gate 26. The check clock 5a is output when the word address of each frame is O, as shown in FIG. Therefore, the successive frame addresses are 3 to 15.
, and when the word address is O, the OR gate 26
A clock is output from the gate and input to one of the OR gates 24.

On the other hand, the comparator 21 compares the magnitude of the output 4a of the counter 4 that provides the read frame address with the output 1a of the counter 1o that provides the write frame address, and when the read at 1 no. That is, in an abnormal state (a state where the write line and the read line intersect), O is applied to the other input of the OR gate 24. At this time,
The load clock 6a is output from the OR gate 24.

The load value 6b loaded at the timing of the load clock 6a is divided into two by the subtracter 29 from the output 4a of the counter 4.
This value is calculated by the comparator 21 and the subtracter 29. Then, the calculated load value is loaded from the subtracter 29 to the counter 10, and the state returns to the state where the intersection of both lines has been corrected.

The conventional memory address control device is configured as described above, and in particular, the address monitoring device 6 therein has a configuration as shown in FIG.
Although the function of monitoring addresses for a period of 5 and correcting abnormal conditions is fast, the configuration of the address monitoring device is that of comparator 21.
．． This has the disadvantage that the subtracter 29 is required, resulting in an increase in the circuit scale and price.

[Object of the Invention] Therefore, an object of the present invention was to solve the above-mentioned drawbacks of the conventional mashing system, and to provide a memory that simplifies the configuration of an address monitoring device in a memory address control device. An object of the present invention is to provide an address control device.

[Summary of the invention] The feature of this invention is that during the period when the memory address goes around,
This is because the address monitoring device is replaced with an address monitoring device that performs one address check and has a simpler configuration than the conventional address monitoring device.

To this end, the configuration of the present invention includes an address detector which receives the output of the first address generation circuit as an input, detects that the address inputted from the address generation circuit is a predetermined value, and outputs the detected value; and an address area detector that receives the output of the address generation circuit as an input, detects that the address input from the address generation circuit is within a predetermined range, and outputs the output, and has an output of the address detector. In case,
And when there is no output from the address area detector, a predetermined value is loaded into the address generation circuit of Era 2.

The above-described features and configuration of the present invention will become clearer from the description of the embodiments given below with reference to the drawings.

[Description of Embodiment] FIG. 6 is a block diagram showing an example of the configuration of an address monitoring device forming a part of an embodiment of the present invention. The configuration of other parts of this embodiment is the same as the conventional device shown in FIG. 1 described above.

-”)'<K Straw, in the block circuit of Fig. 1, a3,
In one embodiment of the present invention, the specific configuration of the address monitoring device 6 is shown in FIG.

Next, the configuration of FIG. 6 will be explained. In Figure 6, 30
is an address detector that detects the read frame address value "3". 31 has a frame address of ``0''.
This is an address area detector that outputs rOJ when the value is other than 2. Further, 36 is an OR gate which receives the output of the address detector 30 and the check clock 5a as input,
37 is the output of the OR gate 36 and the address area detector 31
It is an OR gate whose inputs are the output of In this circuit, the output of the OR gate 37 becomes the load clock 6a,
The load value 6b given to the counter 10 at the timing of the load clock 6a is preset to "1".

Therefore, as is clear from the comparison between FIG. 5 and FIG. 6, in one embodiment of the present invention, the comparator 21 and the subtracter 29 are not required in the address monitoring device, and the circuit configuration can be simplified. There is.

Next, from the operation explanation of the circuit shown in FIG. frame address is 13'' and word)7 dress is ``
A clock is output only when the value is 0. At this time,%
As shown in Figure 1, normal playback occurs when the frame address for writing is from 0 to 2, but noisy noise occurs in other ranges, such as on the read line or write line. are intersected, and correct playback cannot be performed. Therefore,
When such an abnormality occurs, the adjustment area detector 3
1 (address f611 output device 31 outputs rOJ when the frame address is other than "O~2") to "
1'' is output, and the output of the OR gate 36 is sent to the ORG-1 via the 37 as the load clock 6a to the counter 10.
Figure 1). Further, in synchronization with the load clock 6a, a load value 6b of "1" is also given to the counter 10. J: Then, the value of the counter 10 becomes [2-1, and the state returns to the normal state fIi1 as shown in FIG. 4. From then on, the addresses are circulated, and the Minjo state is restored.

In the above embodiment, the detection value of the address detector 30 is "31", and the detection range of the address area detector 31 is "0".
-21, but it may be set to any value as long as both address lines do not cross each other.

Furthermore, the OR gates 36 and 37 can be replaced with other gate circuits depending on the polarity conditions of the elements connected to the input and output.

Furthermore, by adding an external control signal 91 such as a power muting signal used when turning on the power to the output of the address area detector 31, the address relationship can be easily set from the outside. It also has

[Effects of the Invention] According to the above J: according to the present invention, it is possible to provide an address monitoring device with a very simple configuration compared to the configuration of the address monitoring device in the conventional memory address control device U. Therefore, the circuit scale of the memory address control device as a whole can be reduced, and the device can be made at a low cost.

In particular, when the memory address control device is constructed using an LSI, comparators and subtracters having a large number of elements can be omitted, which is very effective.

[Brief explanation of drawings]

FIG. 1J is a block diagram showing the configuration of a conventional address control device. FIG. 2 is an input timing diagram of the write address generation circuit. FIG. 3 is a manual timing diagram of the read address generation circuit. FIG. 4 is a diagram showing an example of a memory map. FIG. 5 is a block diagram showing the configuration of an address monitoring circuit in a conventional address control device. FIG. 6 is a diagram illustrating an example of the configuration of an address monitoring circuit in an embodiment of the present invention. In the figure, 2, 4, 8.10 are counters;
4 constitutes the first address generation circuit. Further, 8 and 10 constitute a second address generation circuit. Furthermore, 11 is a selector, 30 is an Atonenos detector, 3
1 indicates an atl female cell detector. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa-55! :. FIG. Calligraphy (spontaneous) 1. ￥ Director-General of the License Agency 1 Indication of matter A'1 1 No. 1984-161384 2 Name of the invention 3, relationship to the case of the person making the amendment Birth-1, Applicant's address 2 Marunouchi, Chiyoda-ku, Tokyo 1] 2-3 Name (601,) Mitsubishi Electric Corporation Representative Kata 1 + Jinhachibe 4, Agent address 2-2 Marunouchi, Chiyoda-ku, Tokyo: No. 3-%H
i', kai A5-ni! No. 5, Bright IHH to be corrected! Column 6 of Detailed Description of the Invention of J, Contents of Amendment (1) The relationship 1 on page 8, line 6 of the Book of Clearance is maintained. " is corrected to "traverse memory while maintaining relationships." (2) Correct "1 word address" on page 9, line 14 of the specification to "1 frame address". (3) On page 14, line 13 of the specification, 1 to ``1'' is corrected to 1 to ``0''. (4) On page 14, line 19 of the specification, ``The value is ``2'''' is corrected to ``The value is ``1''. 1 step up - hair

Claims (1)

[Claims] First and second memory address generation circuits each manage two systems, and the outputs of the first and second memory address generation circuits are input, and the inputs are selected in a time-sharing manner to generate memory data. In a memory address $IItil+ device including a selector that outputs to an address, the output of the first address generation circuit is input, and it is detected that the address input from the first address generation circuit is a predetermined value. an address detector that outputs a
an address area detector that detects and outputs an address input from an address generation circuit within a predetermined range, and when there is an output of the address detector, and the address area detector A memory address control device, characterized in that when there is no output, a predetermined value is loaded into the second address generation circuit.