JPS5650450A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5650450A
JPS5650450A JP12654979A JP12654979A JPS5650450A JP S5650450 A JPS5650450 A JP S5650450A JP 12654979 A JP12654979 A JP 12654979A JP 12654979 A JP12654979 A JP 12654979A JP S5650450 A JPS5650450 A JP S5650450A
Authority
JP
Japan
Prior art keywords
odd
access
address
addresses
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12654979A
Other languages
Japanese (ja)
Inventor
Mitsuo Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12654979A priority Critical patent/JPS5650450A/en
Publication of JPS5650450A publication Critical patent/JPS5650450A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the processing speed, by making it possible to access odd- even addresses continuously without interleaving by one access instruction.
CONSTITUTION: Memory bank 10 consisting of many memory elements is divided into even address memory block 11 indicated by even addresses and odd address memory block 12 indicated by odd addresses. The access address of bank 10 is set to address register 13, and data output from bank 10 is latched in data register 14. The external indication is generated as a state signal, which can access odd and even addresses, by FFs 21W23 AND gate 24 to control data selectors 15 and 16. Thus, odd-even addresses latched in register 14 can be accessed continuously to improve the processing speed.
COPYRIGHT: (C)1981,JPO&Japio
JP12654979A 1979-10-01 1979-10-01 Memory control system Pending JPS5650450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12654979A JPS5650450A (en) 1979-10-01 1979-10-01 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12654979A JPS5650450A (en) 1979-10-01 1979-10-01 Memory control system

Publications (1)

Publication Number Publication Date
JPS5650450A true JPS5650450A (en) 1981-05-07

Family

ID=14937920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12654979A Pending JPS5650450A (en) 1979-10-01 1979-10-01 Memory control system

Country Status (1)

Country Link
JP (1) JPS5650450A (en)

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