JPS55123721A - Direct memory access unit - Google Patents
Direct memory access unitInfo
- Publication number
- JPS55123721A JPS55123721A JP3043179A JP3043179A JPS55123721A JP S55123721 A JPS55123721 A JP S55123721A JP 3043179 A JP3043179 A JP 3043179A JP 3043179 A JP3043179 A JP 3043179A JP S55123721 A JPS55123721 A JP S55123721A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- signal
- dma
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
PURPOSE: To make it possible to omit the routine for the data check processing on a program by providing a circuit, which detects whether plural linkage data are present or not and controls them, in a DMA circuit.
CONSTITUTION: Data on data bus 7 is inputted to DMA control circuit 3 through interface circuit 2, circuit 3 decides whether the processing across plural bytes is required for this data or not. If this processing is required, holding circuit 31 is set, and simultaneously, the number of required bytes is stored in register circuit 34. Then, a transfer completion signal is outputted from memory control circuit 4 for every transfer completion of one-byte components of data and is counted by counter 33. When this count value agrees with the entry value of register 34, one shot circuit 36 generates a signal due to the output of comparison circuit 35. By this signal S42, memory bus use permission signal S4 and DMA use request signal S3 are released, and CPU 6 can transfer data to and from the memory through memory bus 5.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3043179A JPS55123721A (en) | 1979-03-15 | 1979-03-15 | Direct memory access unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3043179A JPS55123721A (en) | 1979-03-15 | 1979-03-15 | Direct memory access unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55123721A true JPS55123721A (en) | 1980-09-24 |
Family
ID=12303750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3043179A Pending JPS55123721A (en) | 1979-03-15 | 1979-03-15 | Direct memory access unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55123721A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63305446A (en) * | 1987-06-08 | 1988-12-13 | Toshiba Corp | Data transfer control device |
-
1979
- 1979-03-15 JP JP3043179A patent/JPS55123721A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63305446A (en) * | 1987-06-08 | 1988-12-13 | Toshiba Corp | Data transfer control device |
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