JPS55122297A - Memory system - Google Patents

Memory system

Info

Publication number
JPS55122297A
JPS55122297A JP2630479A JP2630479A JPS55122297A JP S55122297 A JPS55122297 A JP S55122297A JP 2630479 A JP2630479 A JP 2630479A JP 2630479 A JP2630479 A JP 2630479A JP S55122297 A JPS55122297 A JP S55122297A
Authority
JP
Japan
Prior art keywords
memory
area
defective
make
accessed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2630479A
Other languages
Japanese (ja)
Inventor
Mitsuo Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2630479A priority Critical patent/JPS55122297A/en
Publication of JPS55122297A publication Critical patent/JPS55122297A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to establish easily data maintenance by locking a defective memory area of a memory and reporting this lock to the access source when the defective memory area of the memory is accessed.
CONSTITUTION: When an area is tried to be accessed where parity error and a memory miss occur frequently in memory system 1, NAND gate 16 is operated by the input of address bus 14 and the output of memory lock register 12, and timing circuit 15 in the memory is interlocked to make read/write impossible. Simultaneously, the memory system itself returns this interlocking to the unit which the system tries to access, so that the program can detect the state os system 1 again to make re-configuration of the memory layout possible. Then, 0 and 1 are set to register 2 correspondingly to the address of system 1 previously, for example, for the good area of system 1 and the defective area of system 1 respectively.
COPYRIGHT: (C)1980,JPO&Japio
JP2630479A 1979-03-07 1979-03-07 Memory system Pending JPS55122297A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2630479A JPS55122297A (en) 1979-03-07 1979-03-07 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2630479A JPS55122297A (en) 1979-03-07 1979-03-07 Memory system

Publications (1)

Publication Number Publication Date
JPS55122297A true JPS55122297A (en) 1980-09-19

Family

ID=12189610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2630479A Pending JPS55122297A (en) 1979-03-07 1979-03-07 Memory system

Country Status (1)

Country Link
JP (1) JPS55122297A (en)

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