JPS55121761A - Frame synchronous circuit for high-speed pcm signal - Google Patents
Frame synchronous circuit for high-speed pcm signalInfo
- Publication number
- JPS55121761A JPS55121761A JP2972279A JP2972279A JPS55121761A JP S55121761 A JPS55121761 A JP S55121761A JP 2972279 A JP2972279 A JP 2972279A JP 2972279 A JP2972279 A JP 2972279A JP S55121761 A JPS55121761 A JP S55121761A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- coincidence
- output
- bit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To secure the synchronism by giving the inversion to the 1/2 division clock via the exclusive OR circuit in case no synchronism is detected for the output of the synchronous detection circuit, thus decreasing the number of the circuit elements rquired. CONSTITUTION:The bit clock supplied from terminal B receives the 1/2 division at FF1 to be used for the input of one side EXOR circuit 14, and the clock of the same or opposite phase C or C' is delivered according to 0 and 1 of the input of the other side each. The synchronous pattern given from terminal A is memorized in shift register 3 with every 1 bit and via clock C; while the synchronous pattern which is delayed by 1 bit at FF2 is memorized is shift register 4 with every 1 bit respectively. The output of both registers 3 and 4 are supplied to coincidence detection circuit 5 for the decision of coincidence with the frame synchronous pattern. With detection of this coincidence, the output of FF10 features 1. And the output of FF13 is inverted to become 1 if no coincidence is detected within the fixed time determined by monostable multivibrator 11. At the same time, the phase of the clock features C' to repeat the action mentioned above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2972279A JPS55121761A (en) | 1979-03-14 | 1979-03-14 | Frame synchronous circuit for high-speed pcm signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2972279A JPS55121761A (en) | 1979-03-14 | 1979-03-14 | Frame synchronous circuit for high-speed pcm signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55121761A true JPS55121761A (en) | 1980-09-19 |
Family
ID=12283995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2972279A Pending JPS55121761A (en) | 1979-03-14 | 1979-03-14 | Frame synchronous circuit for high-speed pcm signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55121761A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6265536A (en) * | 1985-09-17 | 1987-03-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock asynchronizing data detection system |
JPS6265535A (en) * | 1985-09-17 | 1987-03-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock asynchronizing data detection system |
JPS642436A (en) * | 1987-06-25 | 1989-01-06 | Oki Electric Ind Co Ltd | Clock extracting circuit |
-
1979
- 1979-03-14 JP JP2972279A patent/JPS55121761A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6265536A (en) * | 1985-09-17 | 1987-03-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock asynchronizing data detection system |
JPS6265535A (en) * | 1985-09-17 | 1987-03-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock asynchronizing data detection system |
JPS642436A (en) * | 1987-06-25 | 1989-01-06 | Oki Electric Ind Co Ltd | Clock extracting circuit |
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