JPS5687212A - Digital demodulating circuit - Google Patents
Digital demodulating circuitInfo
- Publication number
- JPS5687212A JPS5687212A JP16292779A JP16292779A JPS5687212A JP S5687212 A JPS5687212 A JP S5687212A JP 16292779 A JP16292779 A JP 16292779A JP 16292779 A JP16292779 A JP 16292779A JP S5687212 A JPS5687212 A JP S5687212A
- Authority
- JP
- Japan
- Prior art keywords
- information
- bit
- demodulation clock
- demodulating circuit
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE: To enable high-speed demodulation clock phase control by detecting bit [11] information in two demodulating circuit outputs, by discriminating between bit [1] information and information on a boundary between bits [0] with the detected information, and then by clearing or setting a demodulation clock generator according to the boundary information.
CONSTITUTION: Two demodulating circuits are provided; one circuit is supplied with output Q' of FF, (e) and the other with output Q. Consequently, even if the phase of Q'4A of FF, (e) is inverted to disable one demodulating circuit to obtain detection pulse 5A of bit [1], the other demodulating circuit can obtain detection pulse 5B of bit [1] without fail. For example, pulse 5A with information of bit [1] or/and pulse 5B with the information on the boundary between bits [0] are used to set or/and reset the clock generator. Consequently, phase control over the demodulation clock can be exercised without waiting for the bit [11] information to arrive at any time and even if the demodulation clock gets out of phase, it can be put in proper phase, so that high-speed demodulation clock phase control will be possible.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16292779A JPS5687212A (en) | 1979-12-14 | 1979-12-14 | Digital demodulating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16292779A JPS5687212A (en) | 1979-12-14 | 1979-12-14 | Digital demodulating circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5687212A true JPS5687212A (en) | 1981-07-15 |
JPS6260746B2 JPS6260746B2 (en) | 1987-12-17 |
Family
ID=15763874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16292779A Granted JPS5687212A (en) | 1979-12-14 | 1979-12-14 | Digital demodulating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5687212A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11082271B2 (en) * | 2016-07-01 | 2021-08-03 | Texas Instruments Incorporated | Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop |
-
1979
- 1979-12-14 JP JP16292779A patent/JPS5687212A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11082271B2 (en) * | 2016-07-01 | 2021-08-03 | Texas Instruments Incorporated | Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop |
Also Published As
Publication number | Publication date |
---|---|
JPS6260746B2 (en) | 1987-12-17 |
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