JPS5687212A - Digital demodulating circuit - Google Patents

Abstract

PURPOSE: To enable high-speed demodulation clock phase control by detecting bit [11] information in two demodulating circuit outputs, by discriminating between bit [1] information and information on a boundary between bits [0] with the detected information, and then by clearing or setting a demodulation clock generator according to the boundary information.

CONSTITUTION: Two demodulating circuits are provided; one circuit is supplied with output Q' of FF, (e) and the other with output Q. Consequently, even if the phase of Q'4A of FF, (e) is inverted to disable one demodulating circuit to obtain detection pulse 5A of bit [1], the other demodulating circuit can obtain detection pulse 5B of bit [1] without fail. For example, pulse 5A with information of bit [1] or/and pulse 5B with the information on the boundary between bits [0] are used to set or/and reset the clock generator. Consequently, phase control over the demodulation clock can be exercised without waiting for the bit [11] information to arrive at any time and even if the demodulation clock gets out of phase, it can be put in proper phase, so that high-speed demodulation clock phase control will be possible.

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