JPS55100750A - Digital phase control oscillator - Google Patents
Digital phase control oscillatorInfo
- Publication number
- JPS55100750A JPS55100750A JP817079A JP817079A JPS55100750A JP S55100750 A JPS55100750 A JP S55100750A JP 817079 A JP817079 A JP 817079A JP 817079 A JP817079 A JP 817079A JP S55100750 A JPS55100750 A JP S55100750A
- Authority
- JP
- Japan
- Prior art keywords
- output
- input signal
- circuits
- circuit
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To regenerate an accurate and stable timing signal by detecting a specific phase of an input signal by a differentiating circuit and delay circuit and then by inputting the output to a phase comparator. CONSTITUTION:Slicer circuits 11...14 slice input analog base-band signal a' at a reference level and then output it to level decision gate 15. While differentiating circuit 16 opereates in the rising direction, differenciating circuit 17 is put into operation in the falling direction, and monostable multivibrators 18 and 19 are triggered respectively in the rising and falling directions to generate delay outputs. Then, a specific phase of the input signal is detected by the differential output of the input signal by circuits 16 and 17 and the delay output of the input signal by circuits 18 and 19 and the output is inputted to a phase comparator added to phase control oscillator 23. Consequently, the suppression value of the jitters is set large, so that an accurate and stable timing signal can be regenerated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP817079A JPS55100750A (en) | 1979-01-29 | 1979-01-29 | Digital phase control oscillator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP817079A JPS55100750A (en) | 1979-01-29 | 1979-01-29 | Digital phase control oscillator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55100750A true JPS55100750A (en) | 1980-07-31 |
Family
ID=11685848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP817079A Pending JPS55100750A (en) | 1979-01-29 | 1979-01-29 | Digital phase control oscillator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55100750A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004088913A1 (en) * | 2003-03-31 | 2004-10-14 | Fujitsu Limited | Phase comparison circuit and clock recovery circuit |
-
1979
- 1979-01-29 JP JP817079A patent/JPS55100750A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004088913A1 (en) * | 2003-03-31 | 2004-10-14 | Fujitsu Limited | Phase comparison circuit and clock recovery circuit |
US7634035B2 (en) | 2003-03-31 | 2009-12-15 | Fujitsu Limited | Phase comparison circuit and clock recovery circuit |
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