JPS55100750A - Digital phase control oscillator - Google Patents

Digital phase control oscillator

Info

Publication number
JPS55100750A
JPS55100750A JP817079A JP817079A JPS55100750A JP S55100750 A JPS55100750 A JP S55100750A JP 817079 A JP817079 A JP 817079A JP 817079 A JP817079 A JP 817079A JP S55100750 A JPS55100750 A JP S55100750A
Authority
JP
Japan
Prior art keywords
output
input signal
circuits
circuit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP817079A
Other languages
Japanese (ja)
Inventor
Tatsuo Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP817079A priority Critical patent/JPS55100750A/en
Publication of JPS55100750A publication Critical patent/JPS55100750A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To regenerate an accurate and stable timing signal by detecting a specific phase of an input signal by a differentiating circuit and delay circuit and then by inputting the output to a phase comparator. CONSTITUTION:Slicer circuits 11...14 slice input analog base-band signal a' at a reference level and then output it to level decision gate 15. While differentiating circuit 16 opereates in the rising direction, differenciating circuit 17 is put into operation in the falling direction, and monostable multivibrators 18 and 19 are triggered respectively in the rising and falling directions to generate delay outputs. Then, a specific phase of the input signal is detected by the differential output of the input signal by circuits 16 and 17 and the delay output of the input signal by circuits 18 and 19 and the output is inputted to a phase comparator added to phase control oscillator 23. Consequently, the suppression value of the jitters is set large, so that an accurate and stable timing signal can be regenerated.
JP817079A 1979-01-29 1979-01-29 Digital phase control oscillator Pending JPS55100750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP817079A JPS55100750A (en) 1979-01-29 1979-01-29 Digital phase control oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP817079A JPS55100750A (en) 1979-01-29 1979-01-29 Digital phase control oscillator

Publications (1)

Publication Number Publication Date
JPS55100750A true JPS55100750A (en) 1980-07-31

Family

ID=11685848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP817079A Pending JPS55100750A (en) 1979-01-29 1979-01-29 Digital phase control oscillator

Country Status (1)

Country Link
JP (1) JPS55100750A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004088913A1 (en) * 2003-03-31 2004-10-14 Fujitsu Limited Phase comparison circuit and clock recovery circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004088913A1 (en) * 2003-03-31 2004-10-14 Fujitsu Limited Phase comparison circuit and clock recovery circuit
US7634035B2 (en) 2003-03-31 2009-12-15 Fujitsu Limited Phase comparison circuit and clock recovery circuit

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