JPS56163512A - Digital signal demodulating system - Google Patents

Abstract

PURPOSE:To realize a signal demodulating system which has a high resistance to the dropout, by detecting the synchronous pattern of a shift register to which a synchronous signal is applied and then deciding the phase of a clock pulse. CONSTITUTION:A pulse (f) synchronous with the reverse position of a reproduced signal plus clocks f1 and f2 of a count-down circuit 5 that have a 180 deg. phase shift are applied to shift registers 56 and 58 via a data separating circuit 1, an edge detecting circuit 2 and a monostable multivibrator 3. The outputs of the registers 56 and 58 are applied to pattern coincident circuits 57 and 59, and outputs (p) and (q) are supplied to an OR circuit 60 when the prescribed pattern lines are distributed in the registers 56 and 58. The output (r) of the circuit 60 is applied to a synchronous protecting circuit 61, and the output (z) of the circuit 61 sets the phase of the circuit 5. Thus a correct synchronous pattern is obtained when the prescribed synchronous signal is applied to the registers 56 and 58. In such way, a stable demodulation is possible with a high resistance to the dropout.