JPS5492147A - Generation system for timing signal - Google Patents

Generation system for timing signal

Info

Publication number
JPS5492147A
JPS5492147A JP16028377A JP16028377A JPS5492147A JP S5492147 A JPS5492147 A JP S5492147A JP 16028377 A JP16028377 A JP 16028377A JP 16028377 A JP16028377 A JP 16028377A JP S5492147 A JPS5492147 A JP S5492147A
Authority
JP
Japan
Prior art keywords
rom
information
stored
bit position
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16028377A
Other languages
Japanese (ja)
Other versions
JPS5939043B2 (en
Inventor
Saburo Nishinomiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52160283A priority Critical patent/JPS5939043B2/en
Publication of JPS5492147A publication Critical patent/JPS5492147A/en
Publication of JPS5939043B2 publication Critical patent/JPS5939043B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To fulfill economization with the memory capacity of a ROM reduced remarkably by providing the ROM stored with words which have information forming a timing signal and read-out cycle assignment information.
CONSTITUTION: The circuit consists of the ROM, control circuit CTL, AND gates AGA and AGB, OR gate OG, address register AR, and buffer register BR (O to n and A and B denote cells). Then, the ROM stores sequentially "1" or "0" as data of information equivalent to required timing for respective timing signals TMO to TMn in the direction that the address of the ROM advances corresponding to the bit direction of one word. At a bit position different from bit positions equivalents to TMO to TMn, namely, bit position A, information is stored which changes RMO to TMn in several nanoseconds, and at the other bit position B, "1" when a word includes information changing them in several microseconds or "0" when not is stored.
COPYRIGHT: (C)1979,JPO&Japio
JP52160283A 1977-12-29 1977-12-29 Timing signal generation method Expired JPS5939043B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52160283A JPS5939043B2 (en) 1977-12-29 1977-12-29 Timing signal generation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52160283A JPS5939043B2 (en) 1977-12-29 1977-12-29 Timing signal generation method

Publications (2)

Publication Number Publication Date
JPS5492147A true JPS5492147A (en) 1979-07-21
JPS5939043B2 JPS5939043B2 (en) 1984-09-20

Family

ID=15711632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52160283A Expired JPS5939043B2 (en) 1977-12-29 1977-12-29 Timing signal generation method

Country Status (1)

Country Link
JP (1) JPS5939043B2 (en)

Also Published As

Publication number Publication date
JPS5939043B2 (en) 1984-09-20

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