JPS5489423A - Read data processing system - Google Patents

Read data processing system

Info

Publication number
JPS5489423A
JPS5489423A JP15879177A JP15879177A JPS5489423A JP S5489423 A JPS5489423 A JP S5489423A JP 15879177 A JP15879177 A JP 15879177A JP 15879177 A JP15879177 A JP 15879177A JP S5489423 A JPS5489423 A JP S5489423A
Authority
JP
Japan
Prior art keywords
digit data
data
cpu22
digit
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15879177A
Other languages
Japanese (ja)
Inventor
Toshikazu Katsuki
Hiroyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP15879177A priority Critical patent/JPS5489423A/en
Publication of JPS5489423A publication Critical patent/JPS5489423A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to detect rapidly a transfer error and reduce the load of a CPU by adding a signal, which indicates the error in preceeding data, to next digit data and transferring it in case of the transfer error.
CONSTITUTION: For example, when an error is generated in the third-digit data, FF 332 and 333 of read control circuit 30 lead out "H" continuously unless a read command signal is given from arithmetic processing unit CPU22. Next, when mark reader 21 reads out the fifth-digit timing signal, the fourth-digit data is read in buffer register 38. At this time, when CPU22 issues the read command for the fourth-digit data, the fourth-digit data is transferred to CPU22 bit parallel through AND gates 350 to 359, and simultaneously, "1" which indicates that preceding data (the third-digit data) is a transfer error is outputted from AND gate 35e, and the fourth-digit data with this signal added is given to CPU22.
COPYRIGHT: (C)1979,JPO&Japio
JP15879177A 1977-12-27 1977-12-27 Read data processing system Pending JPS5489423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15879177A JPS5489423A (en) 1977-12-27 1977-12-27 Read data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15879177A JPS5489423A (en) 1977-12-27 1977-12-27 Read data processing system

Publications (1)

Publication Number Publication Date
JPS5489423A true JPS5489423A (en) 1979-07-16

Family

ID=15679412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15879177A Pending JPS5489423A (en) 1977-12-27 1977-12-27 Read data processing system

Country Status (1)

Country Link
JP (1) JPS5489423A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868156A (en) * 1981-10-20 1983-04-22 Hitachi Ltd Integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868156A (en) * 1981-10-20 1983-04-22 Hitachi Ltd Integrated circuit

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