JPS55153027A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS55153027A
JPS55153027A JP6011379A JP6011379A JPS55153027A JP S55153027 A JPS55153027 A JP S55153027A JP 6011379 A JP6011379 A JP 6011379A JP 6011379 A JP6011379 A JP 6011379A JP S55153027 A JPS55153027 A JP S55153027A
Authority
JP
Japan
Prior art keywords
data
register
level
cpu9
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6011379A
Other languages
Japanese (ja)
Inventor
Takuo Toba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6011379A priority Critical patent/JPS55153027A/en
Publication of JPS55153027A publication Critical patent/JPS55153027A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To realize in an easy method an interface in case that two micro central processors for throughput improvement are used, by providing four flip-flops and one two-way register.
CONSTITUTION: To transfer data from central processor (CPU) 10 to CPU9, R-S flip-flop (FF) 2 is set and the output level of FF4 is confirmed next; when it is zero, data are set in register 6. Once the data are set, FF4 is set to level 1 by a strobe signal of a data set. On CPU9 side, on the other hand, detecting the level of FF2 being 1 judges that data have been sent and when the level of FF4 is 1, data in register 6 are fetched and FF4 is reset. In case of the opposite-directional transfer of data, it is similarly processed as mentioned above by FFs 1 and 3 and register 5.
COPYRIGHT: (C)1980,JPO&Japio
JP6011379A 1979-05-15 1979-05-15 Interface circuit Pending JPS55153027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6011379A JPS55153027A (en) 1979-05-15 1979-05-15 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6011379A JPS55153027A (en) 1979-05-15 1979-05-15 Interface circuit

Publications (1)

Publication Number Publication Date
JPS55153027A true JPS55153027A (en) 1980-11-28

Family

ID=13132727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6011379A Pending JPS55153027A (en) 1979-05-15 1979-05-15 Interface circuit

Country Status (1)

Country Link
JP (1) JPS55153027A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217032A (en) * 1982-06-11 1983-12-16 Fuji Electric Co Ltd Terminal interface controlling system by multimicroprocessor
JPS6421663A (en) * 1987-07-17 1989-01-25 Pfu Ltd Information communication processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217032A (en) * 1982-06-11 1983-12-16 Fuji Electric Co Ltd Terminal interface controlling system by multimicroprocessor
JPS6421663A (en) * 1987-07-17 1989-01-25 Pfu Ltd Information communication processing system
JPH056905B2 (en) * 1987-07-17 1993-01-27 Pfu Ltd

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