JPS5482132A - Memory unit - Google Patents
Memory unitInfo
- Publication number
- JPS5482132A JPS5482132A JP14929777A JP14929777A JPS5482132A JP S5482132 A JPS5482132 A JP S5482132A JP 14929777 A JP14929777 A JP 14929777A JP 14929777 A JP14929777 A JP 14929777A JP S5482132 A JPS5482132 A JP S5482132A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- capacity
- ram23
- writing
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To constitute a large-capacity memory unit which is capable of both the reading and writing of a large capacity independently through the simple-structure circuit and by means of the small capacity first-in/first-out memory and the comparatively large-capacity RAM. CONSTITUTION:The primary component parts are large-capacity RAM23 containing 1st and 2nd address counter 21 and 22 plus small-capacity first-in/first-out FIFO memory 24, and memory 23 and 24 can be connected via switch 25 in order to secure the mutual data shift. At the same time, input/output terminal 27 is connected to switch 25, and switch 27 is connected to counter 21 and 22. Thus, RAM23 and memory 24 can be controlled by writing and reading control pulse W and R. And when terminal 26 and 27 are used for the input and output terminals, the writing and reading action are carried out by RAM23 and memory 24 respectively. In case memory 24 is given the reading action and the input and the output are made opposite among terminal 26 and 27, the operations are made opposite between RAM23 and memory 24.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52149297A JPS5822807B2 (en) | 1977-12-14 | 1977-12-14 | memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52149297A JPS5822807B2 (en) | 1977-12-14 | 1977-12-14 | memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5482132A true JPS5482132A (en) | 1979-06-30 |
JPS5822807B2 JPS5822807B2 (en) | 1983-05-11 |
Family
ID=15472077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52149297A Expired JPS5822807B2 (en) | 1977-12-14 | 1977-12-14 | memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5822807B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58146096A (en) * | 1982-02-24 | 1983-08-31 | Mitsubishi Electric Corp | Programmable ring memory |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62185409U (en) * | 1986-05-14 | 1987-11-25 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52123212A (en) * | 1976-04-09 | 1977-10-17 | Kazuhiro Minamachi | System for deleting time distortion of reproduced signal using memory |
-
1977
- 1977-12-14 JP JP52149297A patent/JPS5822807B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52123212A (en) * | 1976-04-09 | 1977-10-17 | Kazuhiro Minamachi | System for deleting time distortion of reproduced signal using memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58146096A (en) * | 1982-02-24 | 1983-08-31 | Mitsubishi Electric Corp | Programmable ring memory |
Also Published As
Publication number | Publication date |
---|---|
JPS5822807B2 (en) | 1983-05-11 |
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