JPS54125072A - Electronic timer device - Google Patents

Electronic timer device

Info

Publication number
JPS54125072A
JPS54125072A JP3276078A JP3276078A JPS54125072A JP S54125072 A JPS54125072 A JP S54125072A JP 3276078 A JP3276078 A JP 3276078A JP 3276078 A JP3276078 A JP 3276078A JP S54125072 A JPS54125072 A JP S54125072A
Authority
JP
Japan
Prior art keywords
register
address
mode
timer
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3276078A
Other languages
Japanese (ja)
Inventor
Takayasu Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3276078A priority Critical patent/JPS54125072A/en
Publication of JPS54125072A publication Critical patent/JPS54125072A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

PURPOSE: To provide a multistage timer device of good operating characteristic by displaying the memory mode of timer information, the assigned address of plural timers according to changeover of call information and time information.
CONSTITUTION: When the mode changeover switch 19 of an input part 18 is changed over to timer information set mode, the storage contents of a mode memory circuit 29 becomes timer information set mode and the time information having been set in an informaton input part 28 via input control circuit 33 is taken into a set register 35 and is displayed in a display device 41 via display selection circuit 34 and display register 40. On the other hand, an address register 39 takes in the youngest address of the empty memory of timer memories 5 thru 13 via memory content storage register 38, set address selection circuit 37, address set circuit 36, has this address displayed in the device 41 via register 40, and sets the time information in timers 5 thru 13 according to the take-in contents from the register 35. The same holds true of the call mode of the contents of the memories, thus the operations are made easy by adequate display.
COPYRIGHT: (C)1979,JPO&Japio
JP3276078A 1978-03-22 1978-03-22 Electronic timer device Pending JPS54125072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3276078A JPS54125072A (en) 1978-03-22 1978-03-22 Electronic timer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3276078A JPS54125072A (en) 1978-03-22 1978-03-22 Electronic timer device

Publications (1)

Publication Number Publication Date
JPS54125072A true JPS54125072A (en) 1979-09-28

Family

ID=12367790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3276078A Pending JPS54125072A (en) 1978-03-22 1978-03-22 Electronic timer device

Country Status (1)

Country Link
JP (1) JPS54125072A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214292A (en) * 1984-04-10 1985-10-26 Sony Corp Program timer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214292A (en) * 1984-04-10 1985-10-26 Sony Corp Program timer

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