JPS5479573A - Electrostatic induction type transistor - Google Patents

Electrostatic induction type transistor

Info

Publication number
JPS5479573A
JPS5479573A JP14750577A JP14750577A JPS5479573A JP S5479573 A JPS5479573 A JP S5479573A JP 14750577 A JP14750577 A JP 14750577A JP 14750577 A JP14750577 A JP 14750577A JP S5479573 A JPS5479573 A JP S5479573A
Authority
JP
Japan
Prior art keywords
epitaxial layer
layer
region
regions
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14750577A
Other languages
Japanese (ja)
Inventor
Eiichi Iwanami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP14750577A priority Critical patent/JPS5479573A/en
Publication of JPS5479573A publication Critical patent/JPS5479573A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To reduce the power consumption of a transistor connected to an epitaxial layer by prescribing the thickness of the epitaxial layer so that when the epitaxial layer as a channel is grown on a semiconductor substrate, an outward diffusion layer from the substrate to the epitaxial layer and a depletion layer expanding from a gate region to a channel region will not overlap.
CONSTITUTION: On N+-type Si substrate 1 as a source region, N--tyep layer 2 as a channel region is epitaxy-grown, where P+-type gate regions 3 and 4, and N+-type drain region 5 between the both and connected to them are diffusion-formed respectively. Next, the entire surface is covered with oxidized film 6, an opening is provided, and Al electrode 7 connected to both regions 3 and 5 is fitted. In this constitution, the thickness of epitaxial layer 2 is so selected that depletion layer 9 generated by regions 3 and 4 and region 8 diffusing toward from substrate 1 into epitaxial layer 2 will not overlap. As a result, when regions 3 and 4 are connected to a lateral PNP bipolar transistor, its base-grounded current amplification factor will nt decrease.
COPYRIGHT: (C)1979,JPO&Japio
JP14750577A 1977-12-08 1977-12-08 Electrostatic induction type transistor Pending JPS5479573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14750577A JPS5479573A (en) 1977-12-08 1977-12-08 Electrostatic induction type transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14750577A JPS5479573A (en) 1977-12-08 1977-12-08 Electrostatic induction type transistor

Publications (1)

Publication Number Publication Date
JPS5479573A true JPS5479573A (en) 1979-06-25

Family

ID=15431876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14750577A Pending JPS5479573A (en) 1977-12-08 1977-12-08 Electrostatic induction type transistor

Country Status (1)

Country Link
JP (1) JPS5479573A (en)

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