JPS5475280A - Junction-type field effect transistor - Google Patents

Junction-type field effect transistor

Info

Publication number
JPS5475280A
JPS5475280A JP14311377A JP14311377A JPS5475280A JP S5475280 A JPS5475280 A JP S5475280A JP 14311377 A JP14311377 A JP 14311377A JP 14311377 A JP14311377 A JP 14311377A JP S5475280 A JPS5475280 A JP S5475280A
Authority
JP
Japan
Prior art keywords
layer
type
junction
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14311377A
Other languages
Japanese (ja)
Inventor
Shuji Kanamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14311377A priority Critical patent/JPS5475280A/en
Publication of JPS5475280A publication Critical patent/JPS5475280A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To ensure the simultaneous and high-density formation of N- and P-type ch JFET's by providing the opposite conduction-type layer to the epitaxial layer to the epitaxial layer on the substrate. CONSTITUTION:The selective diffusion is given to P-type channel layer 13 of N- epitaxial layer 12's element Q2 on P-type substrate 11, and then the channel region of element Q1 is isolated via P<+>-layer 14. Then N<+>-layer 17 and 18 plus P+-layer 19 and 20 are formed to be used as the source and drain layers after the selective formation of P<+> gate 15 and N<+>-gate 16. After this, the electrode is formed as prescribed. In this way, the bipolar JFET's can be formed simultaneously in an easy way on the same substrate and with a high density.
JP14311377A 1977-11-29 1977-11-29 Junction-type field effect transistor Pending JPS5475280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14311377A JPS5475280A (en) 1977-11-29 1977-11-29 Junction-type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14311377A JPS5475280A (en) 1977-11-29 1977-11-29 Junction-type field effect transistor

Publications (1)

Publication Number Publication Date
JPS5475280A true JPS5475280A (en) 1979-06-15

Family

ID=15331204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14311377A Pending JPS5475280A (en) 1977-11-29 1977-11-29 Junction-type field effect transistor

Country Status (1)

Country Link
JP (1) JPS5475280A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800172A (en) * 1987-02-09 1989-01-24 Kabushiki Kaisha Toshiba Manufacturing method for cascaded junction field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800172A (en) * 1987-02-09 1989-01-24 Kabushiki Kaisha Toshiba Manufacturing method for cascaded junction field effect transistor

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