JPS5465490A - Integrated circuit and its manufacture - Google Patents

Integrated circuit and its manufacture

Info

Publication number
JPS5465490A
JPS5465490A JP13234377A JP13234377A JPS5465490A JP S5465490 A JPS5465490 A JP S5465490A JP 13234377 A JP13234377 A JP 13234377A JP 13234377 A JP13234377 A JP 13234377A JP S5465490 A JPS5465490 A JP S5465490A
Authority
JP
Japan
Prior art keywords
layer
poly
metallic silicide
oxide film
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13234377A
Other languages
Japanese (ja)
Other versions
JPS6032976B2 (en
Inventor
Hiroki Muta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13234377A priority Critical patent/JPS6032976B2/en
Publication of JPS5465490A publication Critical patent/JPS5465490A/en
Publication of JPS6032976B2 publication Critical patent/JPS6032976B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To secure a minute structure for the IC without increasing the wiring resistance by forming the gate electrode wiring or element via the poly-Si metallic silicide conversion layer.
CONSTITUTION: Gate oxide film 4 and field oxide film 3 on p-type Si substrate 1 are covered with poly-Si layer 5. Opening 60 and 70 are drilled selectively to resist film 8, and Pt, Mo and the like are sticked about 1000Å to form layer 61 and 71 through the lift-off. Then a heat treatment is given to have conversion 62 and 72 into the metallic silicide, and layer 5 is removed selectively with use of the etching speed difference. The n-type ion is then injected to form the source and the drain 10 and 11, and then MOSIC is formed through the normal method. In this way, the selective etching property is made use of between the poly-Si and the metallic silicide, thus ensuring formation of an ultra-minute pattern of under 1μm with no trouble of the overtching.
COPYRIGHT: (C)1979,JPO&Japio
JP13234377A 1977-11-02 1977-11-02 Integrated circuit manufacturing method Expired JPS6032976B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13234377A JPS6032976B2 (en) 1977-11-02 1977-11-02 Integrated circuit manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13234377A JPS6032976B2 (en) 1977-11-02 1977-11-02 Integrated circuit manufacturing method

Publications (2)

Publication Number Publication Date
JPS5465490A true JPS5465490A (en) 1979-05-26
JPS6032976B2 JPS6032976B2 (en) 1985-07-31

Family

ID=15079111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13234377A Expired JPS6032976B2 (en) 1977-11-02 1977-11-02 Integrated circuit manufacturing method

Country Status (1)

Country Link
JP (1) JPS6032976B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780739A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780739A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof

Also Published As

Publication number Publication date
JPS6032976B2 (en) 1985-07-31

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