JPS5460419A - Power supply circuit - Google Patents

Power supply circuit

Info

Publication number
JPS5460419A
JPS5460419A JP12684577A JP12684577A JPS5460419A JP S5460419 A JPS5460419 A JP S5460419A JP 12684577 A JP12684577 A JP 12684577A JP 12684577 A JP12684577 A JP 12684577A JP S5460419 A JPS5460419 A JP S5460419A
Authority
JP
Japan
Prior art keywords
fet
voltage division
voltage
liquid crystal
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12684577A
Other languages
Japanese (ja)
Other versions
JPS6051717B2 (en
Inventor
Shuichi Torii
Tamotsu Arai
Naotetsu Saga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12684577A priority Critical patent/JPS6051717B2/en
Publication of JPS5460419A publication Critical patent/JPS5460419A/en
Publication of JPS6051717B2 publication Critical patent/JPS6051717B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Liquid Crystal Display Device Control (AREA)
  • Dc-Dc Converters (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE: To prevent the edges from being off in the wave-shape of the driving voltage for a liquid crystal display with a minimized power consumption by means of an insulated gate FET and a switching means for controlling thereof arranged in the voltage division circuit in parallel with resistances.
CONSTITUTION: Resistance R1, R2 and R3 in a voltage division circuit are respectively provided with FET M1, M2 and M3 in parallel, and switches S1, S2 and S3 are provided to control the respective FETs. To output terminals V0 to V3 of the power circuit, connected is a driving circuit for a liquid crystal display. When voltage applied to the display changes, contacts of the switches S1 to S3 are instantaneously switched to the side B thereby causing FET M1 to M3 to turn on. At this moment, voltage division resistances R1 to R3 are connected in parallel to on-state resistance of the FET M1 to M3 so that output impedances lower at respective voltage division points. This reduces the time constant determined by the impedance and the capacity of the liquid crystal display, thus preventing the edges from being taken off in the waveshape of the driving voltage
COPYRIGHT: (C)1979,JPO&Japio
JP12684577A 1977-10-24 1977-10-24 power circuit Expired JPS6051717B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12684577A JPS6051717B2 (en) 1977-10-24 1977-10-24 power circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12684577A JPS6051717B2 (en) 1977-10-24 1977-10-24 power circuit

Publications (2)

Publication Number Publication Date
JPS5460419A true JPS5460419A (en) 1979-05-15
JPS6051717B2 JPS6051717B2 (en) 1985-11-15

Family

ID=14945283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12684577A Expired JPS6051717B2 (en) 1977-10-24 1977-10-24 power circuit

Country Status (1)

Country Link
JP (1) JPS6051717B2 (en)

Also Published As

Publication number Publication date
JPS6051717B2 (en) 1985-11-15

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