JPS5453876A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS5453876A
JPS5453876A JP12024977A JP12024977A JPS5453876A JP S5453876 A JPS5453876 A JP S5453876A JP 12024977 A JP12024977 A JP 12024977A JP 12024977 A JP12024977 A JP 12024977A JP S5453876 A JPS5453876 A JP S5453876A
Authority
JP
Japan
Prior art keywords
layers
oxide film
column direction
continuous
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12024977A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12024977A priority Critical patent/JPS5453876A/en
Publication of JPS5453876A publication Critical patent/JPS5453876A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To reduce the occurrence of defects and increase the scale of integration by forming the drains and sources of the respective memory elements with the impurity doped layers continuous respectively in the column direction and forming the external gates with the conductor layers continuous in the row direction. CONSTITUTION:A thick field oxide film 12 for element isolation is formed on a Si substrate 11 and first polycrystalline Si layers 13 continuous in the column direction to become floating gates are formed therebetween by way of a gate oxide film. Next, the layers 13 are covered with an oxide film and with this and the film 12 as a mask, ions are implated, forming sources 14, drains 15 of a high impurity concentration continuous in the column direction. Therafter, second polycrystalline Si layers 16 which become external gates are formed continuously in the row direction and with these as a mask, etching is performed to self-align the first layer 13, whereby the isolated floating gates are also obtained in the column direction. After these, the surface is covered with a CVD oxide film, and is then opened with contact holes, where A wirings are attached.
JP12024977A 1977-10-06 1977-10-06 Non-volatile semiconductor memory device Pending JPS5453876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12024977A JPS5453876A (en) 1977-10-06 1977-10-06 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12024977A JPS5453876A (en) 1977-10-06 1977-10-06 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5453876A true JPS5453876A (en) 1979-04-27

Family

ID=14781516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12024977A Pending JPS5453876A (en) 1977-10-06 1977-10-06 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5453876A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0109853A2 (en) * 1982-11-23 1984-05-30 American Microsystems, Incorporated Semiconductor memory devices and methods for making the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0109853A2 (en) * 1982-11-23 1984-05-30 American Microsystems, Incorporated Semiconductor memory devices and methods for making the same
EP0109853A3 (en) * 1982-11-23 1985-06-26 American Microsystems, Incorporated Semiconductor memory devices and methods for making the same

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