JPS5447584A - Junction type field effect transistor - Google Patents

Abstract

PURPOSE: To make advantageous use of semiconductor surface and increase mutual conductances by arraying source regions and drain regions in mesh form and yet alternately arraying these so that the drain regions exist around the source regions and the source regions around the drain regions.

CONSTITUTION: An N type layer is vapor grown on a P⁺ semiconductor substrate 11 and P⁺ type regions 16 are diffusion-formed at both end edges, producing an N type region 12 enclosed by these. Next, a multiplicity of P type source regions 13 and drain regions 14 are formed within this island region 12 and all these are arayed in mesh form, with the region 13 and 14 being arrayed longitudinally and corss. And yet these are so arrayed alternately that all the surroundings of one region become other regions. P⁺ type gate regions 15 continuous to the substrate 11 are let to exist between these. The regions 15 are stopped before reaching the bottom of theisland region 12 to flat faced grating form. After these, comb-form electrodes 18 and 19 are mounted to the source regions 13 and drain regions 14 respectively

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