JPS5422164A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5422164A
JPS5422164A JP8665477A JP8665477A JPS5422164A JP S5422164 A JPS5422164 A JP S5422164A JP 8665477 A JP8665477 A JP 8665477A JP 8665477 A JP8665477 A JP 8665477A JP S5422164 A JPS5422164 A JP S5422164A
Authority
JP
Japan
Prior art keywords
semiconductor device
distributing
gold
tin
silver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8665477A
Other languages
Japanese (ja)
Inventor
Osamu Usuda
Tsukasa Hattori
Hiroyuki Baba
Hiroaki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8665477A priority Critical patent/JPS5422164A/en
Publication of JPS5422164A publication Critical patent/JPS5422164A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To increase both the anti-thermal shock and anti-heat fatigue performance by distributing the elements onto the substrate via the alloy layer of gold, tin and silver.
COPYRIGHT: (C)1979,JPO&Japio
JP8665477A 1977-07-21 1977-07-21 Semiconductor device Pending JPS5422164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8665477A JPS5422164A (en) 1977-07-21 1977-07-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8665477A JPS5422164A (en) 1977-07-21 1977-07-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5422164A true JPS5422164A (en) 1979-02-19

Family

ID=13893007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8665477A Pending JPS5422164A (en) 1977-07-21 1977-07-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5422164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999004423A1 (en) * 1997-07-14 1999-01-28 Infineon Technologies Ag Method and device for producing a chip-substrate assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999004423A1 (en) * 1997-07-14 1999-01-28 Infineon Technologies Ag Method and device for producing a chip-substrate assembly
GB2343551A (en) * 1997-07-14 2000-05-10 Infineon Technologies Ag Method and device for producing a chip-substrate assembly
GB2343551B (en) * 1997-07-14 2002-10-30 Infineon Technologies Ag Method and product for producing a chip-substrate connection
US7442582B2 (en) 1997-07-14 2008-10-28 Infineon Technologies Ag Method for producing a chip-substrate connection

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