JPS54152963A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54152963A
JPS54152963A JP6109478A JP6109478A JPS54152963A JP S54152963 A JPS54152963 A JP S54152963A JP 6109478 A JP6109478 A JP 6109478A JP 6109478 A JP6109478 A JP 6109478A JP S54152963 A JPS54152963 A JP S54152963A
Authority
JP
Japan
Prior art keywords
film
lead
bump
prevent
plating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6109478A
Other languages
Japanese (ja)
Inventor
Akihiro Tomosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6109478A priority Critical patent/JPS54152963A/en
Publication of JPS54152963A publication Critical patent/JPS54152963A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked

Abstract

PURPOSE:To prevent an external lead from deteriorating and also to increase certainty by making a connection with a lead Au surface after stacking a Sn-plating film and an Au-plating film on the Au bump of a semiconductor. CONSTITUTION:Au bump 3 is plated with Sn 4 and then with Au 5 so as to prevent the contamination and loss of Sn in a preprocess. On the surface of Cu lead 7 formed on carrier tape 6, Au film 8 is provided and when an Au film is thermally pressure-welded onto the bump, Au film 5 breaks easily, forming Au-Sn junction 9 easily. Further, since the Sn surface is cleans, it is hard enough not to require sintering. In addition, the lead surface, coated with Au layer 8 as well, will never deteriorate.
JP6109478A 1978-05-24 1978-05-24 Semiconductor device Pending JPS54152963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6109478A JPS54152963A (en) 1978-05-24 1978-05-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6109478A JPS54152963A (en) 1978-05-24 1978-05-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54152963A true JPS54152963A (en) 1979-12-01

Family

ID=13161141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6109478A Pending JPS54152963A (en) 1978-05-24 1978-05-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54152963A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105144A (en) * 1993-07-27 1995-04-21 Internatl Business Mach Corp <Ibm> Stacking of circuited polymer dielectric panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105144A (en) * 1993-07-27 1995-04-21 Internatl Business Mach Corp <Ibm> Stacking of circuited polymer dielectric panel

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