JPS54152967A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS54152967A JPS54152967A JP6109578A JP6109578A JPS54152967A JP S54152967 A JPS54152967 A JP S54152967A JP 6109578 A JP6109578 A JP 6109578A JP 6109578 A JP6109578 A JP 6109578A JP S54152967 A JPS54152967 A JP S54152967A
- Authority
- JP
- Japan
- Prior art keywords
- type
- substrate
- assembly efficiency
- manufacture
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE: To prevent n-type inversion and to improve assembly efficiency by previously providing a Cr-Ni-Pd thin film to the reverse surface of a p-type Si substrate and by connecting Au to an Au layer on a support member via Au or an Au-Sn foil.
CONSTITUTION: Adhesion between the p-type Si substrate and Ni is reinforced by Cr, Ni prevents Au immersing into Si, and Pd improves the wetting properties of Ni to Au or Au-Sn. consequently, Au diffuses into p-type Si not to form any n-type inversion layer, and pellet bonding can be done in a contituous furnace, so that assembly efficiency will improve greatly.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6109578A JPS54152967A (en) | 1978-05-24 | 1978-05-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6109578A JPS54152967A (en) | 1978-05-24 | 1978-05-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54152967A true JPS54152967A (en) | 1979-12-01 |
Family
ID=13161171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6109578A Pending JPS54152967A (en) | 1978-05-24 | 1978-05-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54152967A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4293587A (en) * | 1978-11-09 | 1981-10-06 | Zilog, Inc. | Low resistance backside preparation for semiconductor integrated circuit chips |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS518871A (en) * | 1974-07-10 | 1976-01-24 | Hitachi Ltd | Handotaisochino denkyoku |
JPS52107773A (en) * | 1976-03-07 | 1977-09-09 | Toyo Dengu Seisakushiyo Kk | Semiconductor device |
-
1978
- 1978-05-24 JP JP6109578A patent/JPS54152967A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS518871A (en) * | 1974-07-10 | 1976-01-24 | Hitachi Ltd | Handotaisochino denkyoku |
JPS52107773A (en) * | 1976-03-07 | 1977-09-09 | Toyo Dengu Seisakushiyo Kk | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4293587A (en) * | 1978-11-09 | 1981-10-06 | Zilog, Inc. | Low resistance backside preparation for semiconductor integrated circuit chips |
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