JPS54152834A - Program error correcting device - Google Patents

Program error correcting device

Info

Publication number
JPS54152834A
JPS54152834A JP6185678A JP6185678A JPS54152834A JP S54152834 A JPS54152834 A JP S54152834A JP 6185678 A JP6185678 A JP 6185678A JP 6185678 A JP6185678 A JP 6185678A JP S54152834 A JPS54152834 A JP S54152834A
Authority
JP
Japan
Prior art keywords
execution
cpu
program
address
machine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6185678A
Other languages
Japanese (ja)
Inventor
Yoshimi Suzuki
Tetsuo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6185678A priority Critical patent/JPS54152834A/en
Publication of JPS54152834A publication Critical patent/JPS54152834A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To perform the dubug effectively at the execution time of the composite program by combining the support machine to the host machine carrying out the debugged program via the interface.
CONSTITUTION: Program A is carried out by host machine CPU1, and the execution state is monitored by the debug means of CPU1. At the same time, the address of order execution is read into support machine CPU2 through address signal AD and digital input device DI. When the program execution proceeds up to the X address, CPU2 reads in this address via DI and generates interruption signal IT through digital output device DO. As a result, the execution of A is discontinued at CPU1 and execution of B is started. After end of execution of B, the execution of A is restarted. In this case, the program to be debugged is carried out by CPU1 incorporating the complete debug means, thus ensuring much more effective performance than the real machine debug.
COPYRIGHT: (C)1979,JPO&Japio
JP6185678A 1978-05-23 1978-05-23 Program error correcting device Pending JPS54152834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6185678A JPS54152834A (en) 1978-05-23 1978-05-23 Program error correcting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6185678A JPS54152834A (en) 1978-05-23 1978-05-23 Program error correcting device

Publications (1)

Publication Number Publication Date
JPS54152834A true JPS54152834A (en) 1979-12-01

Family

ID=13183155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6185678A Pending JPS54152834A (en) 1978-05-23 1978-05-23 Program error correcting device

Country Status (1)

Country Link
JP (1) JPS54152834A (en)

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