JPS5497344A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS5497344A JPS5497344A JP460978A JP460978A JPS5497344A JP S5497344 A JPS5497344 A JP S5497344A JP 460978 A JP460978 A JP 460978A JP 460978 A JP460978 A JP 460978A JP S5497344 A JPS5497344 A JP S5497344A
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- execution
- halt
- signals
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To debug both hardware and software easily and definitely by sending the 1st and 2nd signals in sequence and by resetting a CPU into a halt state after the CPU executes an instruction starting its execution by the 1st signal.
CONSTITUTION: Through the operation of switch 51, signals are sent out which set run halt R/HFF, thereby allowing the CPU in a halt state to start the execution of a program. Throuth the operation of switch 52, a signal is sent out which resets R/HFF to make the CPU under execution halt, and through the operation of switch 53, the 1st and 2nd signals are sent out in sequence; the execution of the instruction in process of the execution by CPU is executed by the 1st signal and then the CPU is reset into the halt state. Consequently, the checking of hardware and debugging of software can be attained easily and definitely.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP460978A JPS5497344A (en) | 1978-01-18 | 1978-01-18 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP460978A JPS5497344A (en) | 1978-01-18 | 1978-01-18 | Information processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5497344A true JPS5497344A (en) | 1979-08-01 |
Family
ID=11588781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP460978A Pending JPS5497344A (en) | 1978-01-18 | 1978-01-18 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5497344A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58158741A (en) * | 1982-03-12 | 1983-09-21 | Fujitsu Ltd | Instruction processing device |
JPS6052886U (en) * | 1983-09-20 | 1985-04-13 | 株式会社学習研究社 | Game device with pause function |
JPS60106680U (en) * | 1983-12-27 | 1985-07-20 | カシオ計算機株式会社 | electronic game device |
-
1978
- 1978-01-18 JP JP460978A patent/JPS5497344A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58158741A (en) * | 1982-03-12 | 1983-09-21 | Fujitsu Ltd | Instruction processing device |
JPH0150935B2 (en) * | 1982-03-12 | 1989-11-01 | Fujitsu Ltd | |
JPS6052886U (en) * | 1983-09-20 | 1985-04-13 | 株式会社学習研究社 | Game device with pause function |
JPS60106680U (en) * | 1983-12-27 | 1985-07-20 | カシオ計算機株式会社 | electronic game device |
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