JPS5414127A - Test method of memory unit and its unit - Google Patents

Test method of memory unit and its unit

Info

Publication number
JPS5414127A
JPS5414127A JP7947777A JP7947777A JPS5414127A JP S5414127 A JPS5414127 A JP S5414127A JP 7947777 A JP7947777 A JP 7947777A JP 7947777 A JP7947777 A JP 7947777A JP S5414127 A JPS5414127 A JP S5414127A
Authority
JP
Japan
Prior art keywords
unit
test method
error
memory unit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7947777A
Other languages
Japanese (ja)
Inventor
Tsuguhito Serizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7947777A priority Critical patent/JPS5414127A/en
Publication of JPS5414127A publication Critical patent/JPS5414127A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To execute the memory test with high efficiency, by neglecting the error occurrence at the address in which an error is repeatedly appeared on and after the second times, if the error is taken place in an address, and by executing this sequence continuously.
COPYRIGHT: (C)1979,JPO&Japio
JP7947777A 1977-07-05 1977-07-05 Test method of memory unit and its unit Pending JPS5414127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7947777A JPS5414127A (en) 1977-07-05 1977-07-05 Test method of memory unit and its unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7947777A JPS5414127A (en) 1977-07-05 1977-07-05 Test method of memory unit and its unit

Publications (1)

Publication Number Publication Date
JPS5414127A true JPS5414127A (en) 1979-02-02

Family

ID=13690967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7947777A Pending JPS5414127A (en) 1977-07-05 1977-07-05 Test method of memory unit and its unit

Country Status (1)

Country Link
JP (1) JPS5414127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046047A (en) * 1989-02-10 1991-09-03 Plessey Overseas Limited Circuit arrangement for verifying data stored in a random access memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046047A (en) * 1989-02-10 1991-09-03 Plessey Overseas Limited Circuit arrangement for verifying data stored in a random access memory

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