JPS54150970A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54150970A
JPS54150970A JP5962778A JP5962778A JPS54150970A JP S54150970 A JPS54150970 A JP S54150970A JP 5962778 A JP5962778 A JP 5962778A JP 5962778 A JP5962778 A JP 5962778A JP S54150970 A JPS54150970 A JP S54150970A
Authority
JP
Japan
Prior art keywords
film
diffusion
sio
substrate
abnormal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5962778A
Other languages
Japanese (ja)
Inventor
Hiroshi Isaji
Seishi Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5962778A priority Critical patent/JPS54150970A/en
Publication of JPS54150970A publication Critical patent/JPS54150970A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To avoid the abnormal diffusion such as penetration or the like when Sb is diffued selectively onto the Si substrate by covering the areas excluding the diffusion part with the Si3N4 film or the lamination film composed of the lower layer of SiO2 and the upper layer of Si3N4 each.
CONSTITUTION: The SiO2 film is used for the mask when giving the selective diffusion of Sb onto Si substrate 1. In this case, the Sb glass and the SiO2 film are fused together when the Sb amount in the Sb gas exceeds a certain level, an thus Sb penetrates the SiO2 film to cause the abnormal diffusion. In this connection, the Si3N4 film is used for the mask, and the Si3N4 film is liminated on the SiO2 film, when used, to prevent the abnormal diffusion. In other words, SiO2 film 2 and Si3N4 film 3 are coated on Si substrate 1, and opening 4 is provided opposing to the diffusion part. Then Sb glass layer 5 is formed on the entire surface through the solid diffusion or the coating diffusion, and the heat treatment is given in the atmosphere using N2 gas mainly to from diffusion region 6.
COPYRIGHT: (C)1979,JPO&Japio
JP5962778A 1978-05-18 1978-05-18 Manufacture of semiconductor device Pending JPS54150970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5962778A JPS54150970A (en) 1978-05-18 1978-05-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5962778A JPS54150970A (en) 1978-05-18 1978-05-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54150970A true JPS54150970A (en) 1979-11-27

Family

ID=13118651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5962778A Pending JPS54150970A (en) 1978-05-18 1978-05-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54150970A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023203A (en) * 1988-07-28 1991-06-11 Korea Electronics & Telecommunications Research Institute Et Al. Method of patterning fine line width semiconductor topology using a spacer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023203A (en) * 1988-07-28 1991-06-11 Korea Electronics & Telecommunications Research Institute Et Al. Method of patterning fine line width semiconductor topology using a spacer

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