JPS54147786A - Transistor - Google Patents

Transistor

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Publication number
JPS54147786A
JPS54147786A JP5579778A JP5579778A JPS54147786A JP S54147786 A JPS54147786 A JP S54147786A JP 5579778 A JP5579778 A JP 5579778A JP 5579778 A JP5579778 A JP 5579778A JP S54147786 A JPS54147786 A JP S54147786A
Authority
JP
Japan
Prior art keywords
gate
current
punch
controllability
taking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5579778A
Other languages
Japanese (ja)
Inventor
Yasutaka Nakasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP5579778A priority Critical patent/JPS54147786A/en
Publication of JPS54147786A publication Critical patent/JPS54147786A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To remarkably increase the controllability, by taking the implanted construction for the gate, in the MOS type FET operating the punch through current with control. CONSTITUTION:The source region 13 and the drain region 14 are formed on the semiconductor substrate 12, and the gate electrode 19 is coated on the surface of the substrate 12 between those regions via the insulation film 16. In this case, the insulation film 16 and the gate electrode 19 are taken as implanted type, taking the construction that the gate pole 19 is closed to the path of the punch through current 21. Thus, the controllability to the punch through current 21 is very increased, to remarkably increase the leakage current, gate voltage and gate controllability. No problem is taken place even with deeper depth of the implantation than that of the regions 13 and 14, and it can be up to about 4 mum.
JP5579778A 1978-05-11 1978-05-11 Transistor Pending JPS54147786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5579778A JPS54147786A (en) 1978-05-11 1978-05-11 Transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5579778A JPS54147786A (en) 1978-05-11 1978-05-11 Transistor

Publications (1)

Publication Number Publication Date
JPS54147786A true JPS54147786A (en) 1979-11-19

Family

ID=13008895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5579778A Pending JPS54147786A (en) 1978-05-11 1978-05-11 Transistor

Country Status (1)

Country Link
JP (1) JPS54147786A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51114074A (en) * 1975-03-31 1976-10-07 Sony Corp Insulation gate type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51114074A (en) * 1975-03-31 1976-10-07 Sony Corp Insulation gate type field effect transistor

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