JPS54138364A - Alternating current logical sum circuit - Google Patents
Alternating current logical sum circuitInfo
- Publication number
- JPS54138364A JPS54138364A JP4697178A JP4697178A JPS54138364A JP S54138364 A JPS54138364 A JP S54138364A JP 4697178 A JP4697178 A JP 4697178A JP 4697178 A JP4697178 A JP 4697178A JP S54138364 A JPS54138364 A JP S54138364A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- diode
- fed
- alternating current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Abstract
PURPOSE:To avoid stray signal for input AC signals, by using PNP and NPN transistors with emitter common connection and taking AC logc through the coupling of diode to the collector of each transistor. CONSTITUTION:When a signal is fed from the AC input signal 1 at the logical input terminal A, it is given to the collector of the NPN transistor 9 via the diode 3 at positive cycle. On the other hand, positive voltage is fed to the base of the transistor 9 via the resistor 7 from the AC power supply 13, and the transistor 9 is turned on. Next, at negative cycle, it is given to the collector of the PNP transistor 10 via the diode 5. On the other hand, negative voltage is fed to the base of the transistor 10 via the resistor 11, and the transistor 10 is turned on. Further, output voltage is caused at the emitter common junction of the transistor 9 and 10 being the output terminal Y.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4697178A JPS54138364A (en) | 1978-04-19 | 1978-04-19 | Alternating current logical sum circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4697178A JPS54138364A (en) | 1978-04-19 | 1978-04-19 | Alternating current logical sum circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54138364A true JPS54138364A (en) | 1979-10-26 |
JPS6111488B2 JPS6111488B2 (en) | 1986-04-03 |
Family
ID=12762133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4697178A Granted JPS54138364A (en) | 1978-04-19 | 1978-04-19 | Alternating current logical sum circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54138364A (en) |
-
1978
- 1978-04-19 JP JP4697178A patent/JPS54138364A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6111488B2 (en) | 1986-04-03 |
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