JPS54110786A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54110786A
JPS54110786A JP1738778A JP1738778A JPS54110786A JP S54110786 A JPS54110786 A JP S54110786A JP 1738778 A JP1738778 A JP 1738778A JP 1738778 A JP1738778 A JP 1738778A JP S54110786 A JPS54110786 A JP S54110786A
Authority
JP
Japan
Prior art keywords
chip
pattern
solder material
electrode
adhered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1738778A
Other languages
Japanese (ja)
Inventor
Mitsuharu Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP1738778A priority Critical patent/JPS54110786A/en
Publication of JPS54110786A publication Critical patent/JPS54110786A/en
Pending legal-status Critical Current

Links

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE: To avoid the deterioration of the chip and the solder material caused by heat and thus to obtain a highly reliable device by giving the local heating to the area where the semiconductor chip is adhered.
CONSTITUTION: Pattern 3 is formed with gold or the like on alumina support substrate 2 in a larger size than semiconductor chip 1. And solder material 4 smaller than the chip adhering surface is sticked. Parallel gap electric welded electrode 5 is then made to touch the pattern near the both ends of the chip, and the chip is pressed with collet 6 to make electrode 5 conduct. Thus pattern 3 generates heat instantaneously to fuse the solder material, and then the chip is adhered on the pattern by stopping the conduction of the electrode. The solder material is diffused from the center to the periphery of the adhering surface with no sucking of gas or air. Furthermore, the positional accuracy is enhanced, thus preventing the shift of adhesion.
COPYRIGHT: (C)1979,JPO&Japio
JP1738778A 1978-02-17 1978-02-17 Manufacture of semiconductor device Pending JPS54110786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1738778A JPS54110786A (en) 1978-02-17 1978-02-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1738778A JPS54110786A (en) 1978-02-17 1978-02-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54110786A true JPS54110786A (en) 1979-08-30

Family

ID=11942580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1738778A Pending JPS54110786A (en) 1978-02-17 1978-02-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54110786A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078020A (en) * 1996-11-19 2000-06-20 Nec Corporation Apparatus and method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078020A (en) * 1996-11-19 2000-06-20 Nec Corporation Apparatus and method for manufacturing semiconductor device

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