JPS5448173A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5448173A
JPS5448173A JP11485877A JP11485877A JPS5448173A JP S5448173 A JPS5448173 A JP S5448173A JP 11485877 A JP11485877 A JP 11485877A JP 11485877 A JP11485877 A JP 11485877A JP S5448173 A JPS5448173 A JP S5448173A
Authority
JP
Japan
Prior art keywords
film
substrate
etching
container
electrode pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11485877A
Other languages
Japanese (ja)
Inventor
Osamu Shiozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11485877A priority Critical patent/JPS5448173A/en
Publication of JPS5448173A publication Critical patent/JPS5448173A/en
Pending legal-status Critical Current

Links

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To increase the output power capacity by securing a highly efficient heat emission as well as a low junction temperature.
CONSTITUTION: Base electrode pattern 3 and emitter electrode pattern 4 are formed to extend onto first insulating film 2 on semiconductor substrate, and then second insulating film 5 is formed on the entire surface of the substrate. Bonding pad part 3' and 4' are exposed for pattern 3 and 4 respectively, and at the same time an etching is applied to film 5 so that the areas covering stripe part 3' and 4' may remain. After this, metal film 6 is formed through etching so as not to swell out over film 5. The striping is then given to form transistor chip 7 which is mounted to container 8 via bonding. In this case, substrate 1 is mounted to container 8 through the surface to which no film 2 nor film 6 is provided. Finally, heat emission plate 9 featuring an extremely high heat conductivity is positioned to film 6 and then sealed up via sealing material 10 such as the silicone resin, glass or the like with application of appropriate pressure
COPYRIGHT: (C)1979,JPO&Japio
JP11485877A 1977-09-22 1977-09-22 Semiconductor device Pending JPS5448173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11485877A JPS5448173A (en) 1977-09-22 1977-09-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11485877A JPS5448173A (en) 1977-09-22 1977-09-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5448173A true JPS5448173A (en) 1979-04-16

Family

ID=14648454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11485877A Pending JPS5448173A (en) 1977-09-22 1977-09-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5448173A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162353A (en) * 1981-03-31 1982-10-06 Nec Corp Package for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162353A (en) * 1981-03-31 1982-10-06 Nec Corp Package for semiconductor device

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