JPS54107255A - Impurity diffusion method - Google Patents

Impurity diffusion method

Info

Publication number
JPS54107255A
JPS54107255A JP1342278A JP1342278A JPS54107255A JP S54107255 A JPS54107255 A JP S54107255A JP 1342278 A JP1342278 A JP 1342278A JP 1342278 A JP1342278 A JP 1342278A JP S54107255 A JPS54107255 A JP S54107255A
Authority
JP
Japan
Prior art keywords
layer
substrate
impurity
type
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1342278A
Other languages
Japanese (ja)
Inventor
Akihiro Tomosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1342278A priority Critical patent/JPS54107255A/en
Publication of JPS54107255A publication Critical patent/JPS54107255A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE: To diffuse impurity in the Si substrate by subjecting the Si substrate to heat treatment in a high-impurity gas atmosphere after causing a poly-Si thin layer adhere to the surface of the Si substrate.
CONSTITUTION: SiO2 layer 2 is formed on the surface of N-type collector substrate 1, and hole 3 is provided, and p-type impurity is diffused to form p-type base layer 4. At this time, since SiO2 layer 5 is generated on the surface of base layer 4, poly-Si thin layer 7 is caused to adhere to layer 5 by the CVD method after hole 6 is provided. Next, the Si substrate is put in an impurity diffusion furnace, and the high- density diffusion of N-type impurity is performed to form N-type emitter region 8. Next, after SiO2 layer 9 is removed by etching, poly-Si layer 7 is processed into a desired form by photo etching.
COPYRIGHT: (C)1979,JPO&Japio
JP1342278A 1978-02-10 1978-02-10 Impurity diffusion method Pending JPS54107255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1342278A JPS54107255A (en) 1978-02-10 1978-02-10 Impurity diffusion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1342278A JPS54107255A (en) 1978-02-10 1978-02-10 Impurity diffusion method

Publications (1)

Publication Number Publication Date
JPS54107255A true JPS54107255A (en) 1979-08-22

Family

ID=11832686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1342278A Pending JPS54107255A (en) 1978-02-10 1978-02-10 Impurity diffusion method

Country Status (1)

Country Link
JP (1) JPS54107255A (en)

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