JPS5291193A - Forming method of conductor pattern - Google Patents

Forming method of conductor pattern

Info

Publication number
JPS5291193A
JPS5291193A JP735476A JP735476A JPS5291193A JP S5291193 A JPS5291193 A JP S5291193A JP 735476 A JP735476 A JP 735476A JP 735476 A JP735476 A JP 735476A JP S5291193 A JPS5291193 A JP S5291193A
Authority
JP
Japan
Prior art keywords
forming method
conductor pattern
secondary layer
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP735476A
Other languages
Japanese (ja)
Other versions
JPS55845B2 (en
Inventor
Shinji Nagaoka
Tadashi Matsumoto
Akira Demura
Hideki Tsunetsugu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP735476A priority Critical patent/JPS5291193A/en
Publication of JPS5291193A publication Critical patent/JPS5291193A/en
Publication of JPS55845B2 publication Critical patent/JPS55845B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Electric Cables (AREA)

Abstract

PURPOSE: The fine conductive pattern having a high precisensess is easily obtained by applying the primary and the secondary layer having specific characteristics on the substratum and forming the non-electrolytic plating layer after making rough surface on the secondary layer.
COPYRIGHT: (C)1977,JPO&Japio
JP735476A 1976-01-26 1976-01-26 Forming method of conductor pattern Granted JPS5291193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP735476A JPS5291193A (en) 1976-01-26 1976-01-26 Forming method of conductor pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP735476A JPS5291193A (en) 1976-01-26 1976-01-26 Forming method of conductor pattern

Publications (2)

Publication Number Publication Date
JPS5291193A true JPS5291193A (en) 1977-08-01
JPS55845B2 JPS55845B2 (en) 1980-01-10

Family

ID=11663610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP735476A Granted JPS5291193A (en) 1976-01-26 1976-01-26 Forming method of conductor pattern

Country Status (1)

Country Link
JP (1) JPS5291193A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60165787A (en) * 1984-01-26 1985-08-28 リーローナル　インコーポレーテッド Method of producing printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60165787A (en) * 1984-01-26 1985-08-28 リーローナル　インコーポレーテッド Method of producing printed circuit board
JPH0449796B2 (en) * 1984-01-26 1992-08-12 Riiroonaru Inc

Also Published As

Publication number Publication date
JPS55845B2 (en) 1980-01-10

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