JPS52131456A - Forming method of electrode - Google Patents

Forming method of electrode

Info

Publication number
JPS52131456A
JPS52131456A JP4766776A JP4766776A JPS52131456A JP S52131456 A JPS52131456 A JP S52131456A JP 4766776 A JP4766776 A JP 4766776A JP 4766776 A JP4766776 A JP 4766776A JP S52131456 A JPS52131456 A JP S52131456A
Authority
JP
Japan
Prior art keywords
electrode
forming method
foundation layer
forming
nicrome
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4766776A
Other languages
Japanese (ja)
Inventor
Keiji Miyamoto
Hiroshi Kato
Kichiji Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4766776A priority Critical patent/JPS52131456A/en
Publication of JPS52131456A publication Critical patent/JPS52131456A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

PURPOSE: To prevent the side etching of the foundation layer, the deterioration of the junction intensity, the exfoliation of vamp electrode and the corrosion of wiring layer respectively, by forming the electrode in such a way that it may extend up to the area around the mask hole on the foundation layer made of nicrome and gold.
COPYRIGHT: (C)1977,JPO&Japio
JP4766776A 1976-04-28 1976-04-28 Forming method of electrode Pending JPS52131456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4766776A JPS52131456A (en) 1976-04-28 1976-04-28 Forming method of electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4766776A JPS52131456A (en) 1976-04-28 1976-04-28 Forming method of electrode

Publications (1)

Publication Number Publication Date
JPS52131456A true JPS52131456A (en) 1977-11-04

Family

ID=12781602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4766776A Pending JPS52131456A (en) 1976-04-28 1976-04-28 Forming method of electrode

Country Status (1)

Country Link
JP (1) JPS52131456A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308335A (en) * 1987-06-10 1988-12-15 Nec Corp Inspecting method for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308335A (en) * 1987-06-10 1988-12-15 Nec Corp Inspecting method for semiconductor device

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