JPS63308335A - Inspecting method for semiconductor device - Google Patents
Inspecting method for semiconductor deviceInfo
- Publication number
- JPS63308335A JPS63308335A JP62145636A JP14563687A JPS63308335A JP S63308335 A JPS63308335 A JP S63308335A JP 62145636 A JP62145636 A JP 62145636A JP 14563687 A JP14563687 A JP 14563687A JP S63308335 A JPS63308335 A JP S63308335A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- plating
- inspection
- contact resistance
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 11
- 238000007747 plating Methods 0.000 claims abstract description 19
- 239000000126 substance Substances 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000011109 contamination Methods 0.000 claims abstract description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000012360 testing method Methods 0.000 claims description 13
- 239000000523 sample Substances 0.000 claims description 11
- 238000007689 inspection Methods 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 abstract description 4
- 230000002411 adverse Effects 0.000 abstract 1
- 239000000356 contaminant Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 101150006573 PAN1 gene Proteins 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の検査方法に関し、特にＴ Ａ Ｂ
（Ｔａｐｅ Ａｕｔｍａｔｅｄ Ｂｏｎｄｉｎｇ）方
式等のめつきにより接続用電極を形成した半導体装置の
電気的検査を行う半導体装置の検査方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for testing semiconductor devices, and in particular, to a method for testing a semiconductor device.
The present invention relates to a semiconductor device testing method for electrically testing a semiconductor device in which connection electrodes are formed by plating using a (tape automated bonding) method or the like.
一般に、ＴＡＢ方式の半導体装置ではバンブ・リード（
Ｂａｍｐｅｄ Ｌｅａｄ）方式のものを除きチップ側に
１０〜２０μｍの高さの金属バンブを形成する必要があ
る。このバンブの形成方法としては、めっきが用いられ
、めっき用のホトレジスト膜を湿式除去した後、めっき
用電極のエツチングなどの必要な工程を経た後、前記バ
ンブ表面に探針を接触させ、電気的検査を行うという方
法がとられている。Generally, TAB type semiconductor devices use bump leads (
Except for the bumped lead type, it is necessary to form a metal bump with a height of 10 to 20 μm on the chip side. Plating is used to form this bump, and after wet removal of the photoresist film for plating and necessary steps such as etching of the plating electrode, a probe is brought into contact with the bump surface and electrically The method of testing is being taken.
第２図（ａ）〜（Ｃ）は従来のかかる一例を説明するた
めの検査工程順に示したバンブ構造を有する半導体装置
の断面図である。FIGS. 2(a) to 2(C) are cross-sectional views of a semiconductor device having a bump structure shown in the order of inspection steps to explain one conventional example.
第２図（ａ）に示すように、半導体装置はまず半導体基
板１上にめっき用電極金属２が被着され、その上にホト
レジスト膜５を被覆する。次に、このホトレジスト膜５
の所定個所を開口し、めっきにより形成する電極（以下
、バンブと称す）３を被着する。As shown in FIG. 2(a), in the semiconductor device, a plating electrode metal 2 is first deposited on a semiconductor substrate 1, and then a photoresist film 5 is coated thereon. Next, this photoresist film 5
Openings are made at predetermined locations, and electrodes (hereinafter referred to as bumps) 3 formed by plating are deposited.
次に、第２図（ｂ）に示すように、ホトレジスト膜５お
よびバンプ３が形成されていない不要のめっき用電極金
属２を除去する。尚、６はバンプ３の表面に形成される
汚染・変質物質である。Next, as shown in FIG. 2(b), the unnecessary plating electrode metal 2 on which the photoresist film 5 and the bumps 3 are not formed is removed. Note that 6 is a contaminant/altered substance formed on the surface of the bump 3.
次に、第２図（Ｃ）に示すように、前記汚染・変質物質
６が形成されたバンプ３に電気検査用の探針４を接触さ
せ、前記半導体装置としての電気的検査を行っている。Next, as shown in FIG. 2(C), an electrical inspection probe 4 is brought into contact with the bump 3 on which the contaminated/altered substance 6 is formed, and an electrical inspection of the semiconductor device is performed. .
上述した従来の検査方法においては、めっきにより形成
されたバンプ表面は面が比較的粗いため、ホトレジスト
膜除去の際の湿式処理による有機物の再付着や後工程の
エツチング処理等による表面の変質などが生じ易かった
。このためバンプに探針を接触させて電気的検査を行う
と、探針とパン１間の接触抵抗が数オームから数十オー
ムにまで達することがある。この抵抗により半導体装置
の電気的検査における数値上の誤差が生じ、はなはだし
い場合には表面物質のみのために特性上本来良品のもの
を不良と判定してしまうという問題がある。In the conventional inspection method described above, the surface of the bump formed by plating is relatively rough, so organic matter may be re-attached due to wet processing when removing the photoresist film, or surface deterioration may occur due to etching treatment in the post-process. It was easy to occur. Therefore, when an electrical test is performed by bringing a probe into contact with a bump, the contact resistance between the probe and the pan 1 may reach several ohms to several tens of ohms. This resistance causes numerical errors in electrical testing of semiconductor devices, and in extreme cases, there is a problem in that a device that is originally good due to its characteristics may be determined to be defective due to only the surface material.
更に、この問題の解決法として探針をセラミック板など
で頻繁に研磨しつつ検査を行なう方法がとられているが
、この場合は探針の摩耗が激しいだけで接触抵抗低減に
は十分でないという不都合があった。Furthermore, a method to solve this problem is to frequently polish the probe with a ceramic plate while performing inspections, but this only causes severe wear on the probe and is not sufficient to reduce contact resistance. There was an inconvenience.
本発明の目的は、かかるめっきにより形成された電極を
有する半導体装置の電気的検査を行うにあたり、接触抵
抗の増加をおさえ正確に且つ容易に実施しうる半導体装
置の検査方法を提供することにある。An object of the present invention is to provide a method for testing a semiconductor device that can be accurately and easily performed while suppressing an increase in contact resistance when electrically testing a semiconductor device having an electrode formed by such plating. .
本発明は、めっきにより外部との接続用電極を半導体基
板上に形成した半導体装置を酸素を含むプラズマ中もし
くはオゾン雰囲気中に曝し、電極表面の汚染・変質物等
を除去する工程と、続いて前記電極に検査用探針を接触
させ前記半導体装置の電気的検査を行う工程とを含んで
構成される。The present invention involves a step of exposing a semiconductor device in which electrodes for connection with the outside are formed on a semiconductor substrate by plating to an oxygen-containing plasma or an ozone atmosphere to remove contamination, altered substances, etc. from the electrode surface; The method includes the step of electrically testing the semiconductor device by bringing a testing probe into contact with the electrode.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するためのバンプ構造
を有する半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device having a bump structure for explaining one embodiment of the present invention.
第１図に示すように、まずホトレジスト膜をマスクにし
て半導体基板１のメッキ用金属２上にバンプ３をめっき
により形成する工程と、しかる後ホトレジスト膜（第２
図（ａ）の５）を除去し、めっき用金属２の不要部分を
エツチングにより除去する工程とは従来と同様である。As shown in FIG. 1, first, a step of forming bumps 3 on the plating metal 2 of the semiconductor substrate 1 by plating using a photoresist film as a mask, and then a step of forming bumps 3 on the plating metal 2 of the semiconductor substrate 1 using the photoresist film as a mask.
The steps of removing 5) in Figure (a) and removing unnecessary portions of the plating metal 2 by etching are the same as in the conventional method.
従来は、このままこの半導体装置のバンプ表面に金属探
針を接触させ電気的検査を行なうが、この際バンプ表面
にはホトレジスト膜の再付着物やめつき用金属のエツチ
ングやその後の水洗によるバンブ表面の汚染や変質物の
ために探針との接触抵抗が数オーム−数十オームに達し
、正確な検査を阻害している。またホトレジスト膜の除
去を湿式及び乾式（酸素プラズマ等）の併用により行い
、再付着物の除去を行なった場合でも、その後の汚染・
変質物の影響が避けられず、接触抵抗の増加を生じてい
る。Conventionally, electrical inspection is carried out by bringing a metal probe into contact with the bump surface of this semiconductor device, but at this time, the bump surface is free from re-deposition of the photoresist film, etching of the metal for polishing, and subsequent washing with water. Contact resistance with the probe reaches several to tens of ohms due to contamination and altered substances, impeding accurate inspection. Furthermore, even if the photoresist film is removed using a combination of wet and dry methods (oxygen plasma, etc.) to remove re-deposition, subsequent contamination and
The influence of altered substances cannot be avoided, resulting in an increase in contact resistance.
本発明においては、電気的検査の直前に半導体装置を、
例えば６００〜９００Ｗ、６０分の酸素プラズマ中に曝
し、表面物質を除去する工程を実施することにある。こ
れにより、接触抵抗に悪影響を与える汚染・再付着物・
変質物が実質的に除去される。In the present invention, the semiconductor device is inspected immediately before electrical inspection.
For example, a step of removing surface substances is carried out by exposing to oxygen plasma at 600 to 900 W for 60 minutes. This causes contamination, redeposit, and
Altered materials are substantially removed.
この後、直ちに電気的測定を行なえば接触抵抗はおおむ
ね５オーム以下に保つことができ、正確な測定・検査が
可能となる。If electrical measurements are made immediately after this, the contact resistance can be maintained at about 5 ohms or less, allowing accurate measurements and inspections.
また、前述の実施例における酸素プラズマに代えて、常
圧・常温のオゾン雰囲気中に例えば６０分曝しても同様
に電極表面の汚染物質等を除去し、接触抵抗のきわめて
少ない電気的検査を実施することも可能である。In addition, instead of using oxygen plasma in the above-mentioned example, even if the electrode is exposed to an ozone atmosphere at normal pressure and temperature for 60 minutes, contaminants etc. on the electrode surface can be removed in the same way, and electrical tests with extremely low contact resistance can be performed. It is also possible to do so.
以上説明した様に、本発明はめっきにより形成された電
極を酸素を含むプラズマ中もしくはオゾン雰囲気中に曝
し表面物質を除去することにより、半導体装置に対する
接触抵抗をおさえ、正確に且つ容易に電気的検査を行う
ことができるという効果がある。As explained above, the present invention exposes electrodes formed by plating to oxygen-containing plasma or ozone atmosphere to remove surface materials, thereby suppressing contact resistance to semiconductor devices and accurately and easily electrically connecting them. This has the effect of allowing inspection to be carried out.
第１図は本発明の一実施例を説明するためのバンプ構造
を有する半導体装置の断面図、第２図（ａ）〜（ｃ）は
従来の一例を説明するための検査工程順に示したバンプ
構造を有する半導体装置の断面図である。
１・・・半導体基板、２・・・めっき用電極金属、３・
・・バンブ、４・・・電気検査用探針。
代理人 弁理士 内 原 晋（′−：第１図
第２図FIG. 1 is a sectional view of a semiconductor device having a bump structure for explaining an embodiment of the present invention, and FIGS. 2(a) to (c) are bumps shown in the order of inspection steps for explaining a conventional example. 1 is a cross-sectional view of a semiconductor device having a structure. 1... Semiconductor substrate, 2... Electrode metal for plating, 3...
... Bamboo, 4... Probe for electrical inspection. Agent: Susumu Uchihara, patent attorney ('-: Figure 1 Figure 2
Claims (1)
した半導体装置を酸素を含むプラズマ中もしくはオゾン
雰囲気中に曝し、電極表面の汚染・変質物等を除去する
工程と、続いて前記電極に検査用探針を接触させ前記半
導体装置の電気的検査を行う工程とを含むことを特徴と
する半導体装置の検査方法。A semiconductor device in which electrodes for connection with the outside are formed on a semiconductor substrate by plating is exposed to an oxygen-containing plasma or an ozone atmosphere to remove contamination and altered substances from the electrode surface, and then the electrode is inspected. A method for testing a semiconductor device, comprising the step of electrically testing the semiconductor device by bringing a probe into contact with the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145636A JPH06105735B2 (en) | 1987-06-10 | 1987-06-10 | Semiconductor device inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145636A JPH06105735B2 (en) | 1987-06-10 | 1987-06-10 | Semiconductor device inspection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63308335A true JPS63308335A (en) | 1988-12-15 |
| JPH06105735B2 JPH06105735B2 (en) | 1994-12-21 |
Family
ID=15389593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62145636A Expired - Fee Related JPH06105735B2 (en) | 1987-06-10 | 1987-06-10 | Semiconductor device inspection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06105735B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147571A (en) * | 1974-10-22 | 1976-04-23 | Central Glass Co Ltd | |
| JPS52131456A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Forming method of electrode |
-
1987
- 1987-06-10 JP JP62145636A patent/JPH06105735B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147571A (en) * | 1974-10-22 | 1976-04-23 | Central Glass Co Ltd | |
| JPS52131456A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Forming method of electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06105735B2 (en) | 1994-12-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |