JPS5024231B1 - - Google Patents

Info

Publication number
JPS5024231B1
JPS5024231B1 JP46059668A JP5966871A JPS5024231B1 JP S5024231 B1 JPS5024231 B1 JP S5024231B1 JP 46059668 A JP46059668 A JP 46059668A JP 5966871 A JP5966871 A JP 5966871A JP S5024231 B1 JPS5024231 B1 JP S5024231B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP46059668A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS5024231B1 publication Critical patent/JPS5024231B1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10W10/041—
    • H10W10/40—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/98—Utilizing process equivalents or options

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
JP46059668A 1970-08-10 1971-08-09 Pending JPS5024231B1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6243770A 1970-08-10 1970-08-10

Publications (1)

Publication Number Publication Date
JPS5024231B1 true JPS5024231B1 (ja) 1975-08-14

Family

ID=22042478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP46059668A Pending JPS5024231B1 (ja) 1970-08-10 1971-08-09

Country Status (8)

Country Link
US (2) US3825450A (ja)
JP (1) JPS5024231B1 (ja)
BE (1) BE771137A (ja)
CA (1) CA931665A (ja)
DE (6) DE2140043A1 (ja)
FR (1) FR2102152A1 (ja)
GB (1) GB1365159A (ja)
NL (1) NL7111014A (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911559A (en) * 1973-12-10 1975-10-14 Texas Instruments Inc Method of dielectric isolation to provide backside collector contact and scribing yield
US4573257A (en) * 1984-09-14 1986-03-04 Motorola, Inc. Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
JPS61166071A (ja) * 1985-01-17 1986-07-26 Toshiba Corp 半導体装置及びその製造方法
US7687887B1 (en) * 2006-12-01 2010-03-30 National Semiconductor Corporation Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter
DE102007010563A1 (de) * 2007-02-22 2008-08-28 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Selektives Wachstum von polykristallinem siliziumhaltigen Halbleitermaterial auf siliziumhaltiger Halbleiteroberfläche

Also Published As

Publication number Publication date
GB1365159A (en) 1974-08-29
DE7130637U (de) 1971-12-02
US3825450A (en) 1974-07-23
FR2102152A1 (ja) 1972-04-07
DE2140054A1 (de) 1972-02-17
DE2140043A1 (de) 1972-02-17
BE771137A (fr) 1972-02-10
DE7130660U (de) 1971-12-02
CA931665A (en) 1973-08-07
US3825451A (en) 1974-07-23
DE2140012A1 (de) 1972-02-17
DE2140023A1 (de) 1972-02-17
NL7111014A (ja) 1972-02-14

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