JPS5024079A - - Google Patents

Info

Publication number
JPS5024079A
JPS5024079A JP49054625A JP5462574A JPS5024079A JP S5024079 A JPS5024079 A JP S5024079A JP 49054625 A JP49054625 A JP 49054625A JP 5462574 A JP5462574 A JP 5462574A JP S5024079 A JPS5024079 A JP S5024079A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP49054625A
Other versions
JPS5546060B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS5024079A publication Critical patent/JPS5024079A/ja
Publication of JPS5546060B2 publication Critical patent/JPS5546060B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10P50/282—
    • H10W20/092—
    • H10W20/40—
    • H10W20/42—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP5462574A 1973-06-29 1974-05-17 Expired JPS5546060B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00375298A US3804738A (en) 1973-06-29 1973-06-29 Partial planarization of electrically insulative films by resputtering

Publications (2)

Publication Number Publication Date
JPS5024079A true JPS5024079A (ja) 1975-03-14
JPS5546060B2 JPS5546060B2 (ja) 1980-11-21

Family

ID=23480308

Family Applications (2)

Application Number Title Priority Date Filing Date
JP5462574A Expired JPS5546060B2 (ja) 1973-06-29 1974-05-17
JP3279580A Granted JPS55130147A (en) 1973-06-29 1980-03-17 Multilayer wired integrated circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP3279580A Granted JPS55130147A (en) 1973-06-29 1980-03-17 Multilayer wired integrated circuit

Country Status (7)

Country Link
US (1) US3804738A (ja)
JP (2) JPS5546060B2 (ja)
CA (1) CA1030665A (ja)
DE (1) DE2430692C2 (ja)
FR (1) FR2235481B1 (ja)
GB (1) GB1418278A (ja)
IT (1) IT1010165B (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432091A (en) * 1977-08-15 1979-03-09 Nec Corp Radar interference eleimenating system
JPS5440079A (en) * 1977-09-05 1979-03-28 Fujitsu Ltd Plasma etching method
JPS54159662A (en) * 1978-06-07 1979-12-17 Hitachi Ltd Method of connecting wire conductors

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5639020B2 (ja) * 1973-10-05 1981-09-10
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4036723A (en) * 1975-08-21 1977-07-19 International Business Machines Corporation RF bias sputtering method for producing insulating films free of surface irregularities
US4007103A (en) * 1975-10-14 1977-02-08 Ibm Corporation Planarizing insulative layers by resputtering
DD136670A1 (de) * 1976-02-04 1979-07-18 Rudolf Sacher Verfahren und vorrichtung zur herstellung von halbleiterstrukturen
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
FR2375718A1 (fr) * 1976-12-27 1978-07-21 Radiotechnique Compelec Dispositif semiconducteur a reseau d'interconnexions multicouche
DE2705611A1 (de) * 1977-02-10 1978-08-17 Siemens Ag Verfahren zum bedecken einer auf einem substrat befindlichen ersten schicht oder schichtenfolge mit einer weiteren zweiten schicht durch aufsputtern
NL7701559A (nl) * 1977-02-15 1978-08-17 Philips Nv Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon.
US4111775A (en) * 1977-07-08 1978-09-05 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Multilevel metallization method for fabricating a metal oxide semiconductor device
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
US4289834A (en) * 1977-10-20 1981-09-15 Ibm Corporation Dense dry etched multi-level metallurgy with non-overlapped vias
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
JPS5893354A (ja) * 1981-11-30 1983-06-03 Mitsubishi Electric Corp 半導体装置の製造法
US4396458A (en) * 1981-12-21 1983-08-02 International Business Machines Corporation Method for forming planar metal/insulator structures
JPS59200440A (ja) * 1983-04-28 1984-11-13 Agency Of Ind Science & Technol 配線構造の製造方法
US4470874A (en) * 1983-12-15 1984-09-11 International Business Machines Corporation Planarization of multi-level interconnected metallization system
JPH0618194B2 (ja) * 1984-07-21 1994-03-09 工業技術院長 段差の被覆方法
JPH0697660B2 (ja) * 1985-03-23 1994-11-30 日本電信電話株式会社 薄膜形成方法
US4756810A (en) * 1986-12-04 1988-07-12 Machine Technology, Inc. Deposition and planarizing methods and apparatus
US5256594A (en) * 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
US5855966A (en) * 1997-11-26 1999-01-05 Eastman Kodak Company Method for precision polishing non-planar, aspherical surfaces
US12057317B2 (en) * 2021-07-19 2024-08-06 Micron Technology, Inc. Conductive layers in memory array region and methods for forming the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3514844A (en) * 1967-12-26 1970-06-02 Hughes Aircraft Co Method of making field-effect device with insulated gate
US3549876A (en) * 1968-03-07 1970-12-22 Eaton Yale & Towne Crane operating radius indicator
FR2119930B1 (ja) * 1970-12-31 1974-08-19 Ibm
DE2202077A1 (de) * 1971-05-17 1972-11-30 Hochvakuum Dresden Veb Verfahren zur Herstellung von Mehrlagenleiterplatten

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432091A (en) * 1977-08-15 1979-03-09 Nec Corp Radar interference eleimenating system
JPS5440079A (en) * 1977-09-05 1979-03-28 Fujitsu Ltd Plasma etching method
JPS54159662A (en) * 1978-06-07 1979-12-17 Hitachi Ltd Method of connecting wire conductors

Also Published As

Publication number Publication date
CA1030665A (en) 1978-05-02
US3804738A (en) 1974-04-16
JPS5546060B2 (ja) 1980-11-21
JPS5623302B2 (ja) 1981-05-30
DE2430692C2 (de) 1982-10-21
FR2235481A1 (ja) 1975-01-24
DE2430692A1 (de) 1975-01-16
JPS55130147A (en) 1980-10-08
IT1010165B (it) 1977-01-10
FR2235481B1 (ja) 1976-07-16
GB1418278A (en) 1975-12-17

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