JPH1197392A - 微細窪みの充填方法及び装置 - Google Patents

微細窪みの充填方法及び装置

Info

Publication number
JPH1197392A
JPH1197392A JP9269306A JP26930697A JPH1197392A JP H1197392 A JPH1197392 A JP H1197392A JP 9269306 A JP9269306 A JP 9269306A JP 26930697 A JP26930697 A JP 26930697A JP H1197392 A JPH1197392 A JP H1197392A
Authority
JP
Japan
Prior art keywords
ultrafine particles
fine
filling
semiconductor substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9269306A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1197392A5 (https=
Inventor
Naoaki Kogure
直明 小榑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Priority to JP9269306A priority Critical patent/JPH1197392A/ja
Publication of JPH1197392A publication Critical patent/JPH1197392A/ja
Publication of JPH1197392A5 publication Critical patent/JPH1197392A5/ja
Pending legal-status Critical Current

Links

Landscapes

  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
JP9269306A 1997-09-16 1997-09-16 微細窪みの充填方法及び装置 Pending JPH1197392A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9269306A JPH1197392A (ja) 1997-09-16 1997-09-16 微細窪みの充填方法及び装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9269306A JPH1197392A (ja) 1997-09-16 1997-09-16 微細窪みの充填方法及び装置

Publications (2)

Publication Number Publication Date
JPH1197392A true JPH1197392A (ja) 1999-04-09
JPH1197392A5 JPH1197392A5 (https=) 2004-10-14

Family

ID=17470512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9269306A Pending JPH1197392A (ja) 1997-09-16 1997-09-16 微細窪みの充填方法及び装置

Country Status (1)

Country Link
JP (1) JPH1197392A (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001027983A1 (en) * 1999-10-15 2001-04-19 Ebara Corporation Method and apparatus for forming interconnection
WO2001084610A1 (fr) * 2000-05-02 2001-11-08 Catalysts & Chemicals Industries Co., Ltd. Procede de realisation d'un circuit integre, et substrat dote d'un circuit integre forme a l'aide dudit procede
JP2003257890A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 物質充填方法、膜形成方法、デバイスおよびデバイスの製造方法
JP2005039261A (ja) * 2003-06-30 2005-02-10 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法及び表示装置の作製方法
KR100597348B1 (ko) 2003-08-12 2006-07-10 세이코 엡슨 가부시키가이샤 배선 패턴의 형성 방법, 반도체 장치의 제조 방법, 전기광학 장치 및 전자 기기

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593952A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd アルミニウム配線層の形成方法
JPH09134891A (ja) * 1995-09-06 1997-05-20 Vacuum Metallurgical Co Ltd 半導体基板への薄膜形成方法
JPH09162288A (ja) * 1995-12-12 1997-06-20 Matsushita Electric Ind Co Ltd 配線構造およびその形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593952A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd アルミニウム配線層の形成方法
JPH09134891A (ja) * 1995-09-06 1997-05-20 Vacuum Metallurgical Co Ltd 半導体基板への薄膜形成方法
JPH09162288A (ja) * 1995-12-12 1997-06-20 Matsushita Electric Ind Co Ltd 配線構造およびその形成方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001027983A1 (en) * 1999-10-15 2001-04-19 Ebara Corporation Method and apparatus for forming interconnection
US6730596B1 (en) 1999-10-15 2004-05-04 Ebara Corporation Method of and apparatus for forming interconnection
WO2001084610A1 (fr) * 2000-05-02 2001-11-08 Catalysts & Chemicals Industries Co., Ltd. Procede de realisation d'un circuit integre, et substrat dote d'un circuit integre forme a l'aide dudit procede
EP1280193A4 (en) * 2000-05-02 2006-01-04 Catalysts & Chem Ind Co METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND SUBSTRATE WITH INTEGRATED CIRCUIT CREATED BY THE METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT
US7163892B2 (en) 2000-05-02 2007-01-16 Catalysts & Chemicals Industries Co., Ltd. Process for producing integrated circuit, and substrate with integrated circuit
KR100805128B1 (ko) 2000-05-02 2008-02-21 쇼꾸바이 카세이 고교 가부시키가이샤 집적 회로의 제조방법 및 집적 회로의 제조방법에 의해형성된 집적 회로를 지닌 기판
JP4578755B2 (ja) * 2000-05-02 2010-11-10 日揮触媒化成株式会社 集積回路の製造方法
JP2003257890A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 物質充填方法、膜形成方法、デバイスおよびデバイスの製造方法
JP2005039261A (ja) * 2003-06-30 2005-02-10 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法及び表示装置の作製方法
KR100597348B1 (ko) 2003-08-12 2006-07-10 세이코 엡슨 가부시키가이샤 배선 패턴의 형성 방법, 반도체 장치의 제조 방법, 전기광학 장치 및 전자 기기

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