JPH1166134A - Printed wiring board design development support system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To support the printed wiring board design development (CAD for PCB) system and to previously check design specifications by generating a dummy net list. SOLUTION: A dummy net list generation part 2 analyzes the dummy net into the correlation of component-pin arrangement positions, etc., when there is not pin-to-pin connection information between mounted components in PCB specifications. A pattern distribution analysis part 3 registers checked cut line coordinates and the number of pattern cuts in each table, a channel capacity analysis part 4 analyzes the empty channel capacity of a single signal layer, and a channel specification distribution analysis part 6 represents as a percent the quotient between the number of pattern cuts and interconnectable length on a virtual cut line and analyzes it as the rate of channel use on an investigation line. Wiring length analysis 7 analyzes Manhattan line length equal to the sum of divided values of pin-to-pin line length. A channel use rate analysis part 8 analyzes the product of the wirable length of the single signal layer and the number of signal layers as the interconnectable length of all the signal layers and an analysis result output part 9 visualize and outputs the respective results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a printed wiring board design development support system (hereinafter simply referred to as a PCB CAD system).

[0002]

2. Description of the Related Art Semiconductor technology, in particular, semiconductor integrated circuits (I
C) Advances in technology have led to the application of electronics technology to most devices. This electronic circuit is generally configured by arranging various active and passive electronic components on a printed wiring board (PCB or PWB) and connecting them by soldering.

[0003] As electronic application equipment becomes more sophisticated, PCB design becomes more and more complicated, and it takes time and effort for designers to design manually, and the designed PCB operates normally without any problem. It is very difficult to design. Therefore, we use a CAD system for PCB,
Using various data stored in this system,
It is common to design a PCB efficiently and with high quality in cooperation with an operator (designer).

A conventional example of such a CAD system for PCB is disclosed in Japanese Patent Laid-Open No. 4-111400. This publication discloses a printed circuit board component placement evaluation method. In order to analyze an accurate evaluation value (temporary wiring length expected value), a temporary wiring path in consideration of the characteristics of an actual wiring algorithm is used as information before wiring. Is determined.

According to this conventional technique, a channel that cannot be wired is read from the board information and registered in a table that holds free channel information. In addition, a flag indicating that the component is directly below the component is set, the component directly below the component and the total number of free channels other than the component are counted for each divided area, and the wiring possibility immediately below the component and the wiring frequency coefficient for each layer are input from the board information. Then, the total length of free channels in the divided area is totaled for each path.

[0006]

The above-mentioned prior art has the following problems or problems to be solved. First, since the channel usage rate in all layers is output only as numerical data as the evaluation value of the pattern congestion degree, it is not possible to recognize which part of the printed circuit board has the pattern concentration. Therefore, it is impossible to reflect it in the wiring design. In other words, there is a drawback that only the quality of the current specific arrangement can be evaluated, and it does not support relocation design for equalizing the pattern distribution.

Next, since the provisional wiring is specified in consideration of the characteristics of the actual wiring algorithm, a processing turnaround time (TAT) equivalent to the automatic wiring is eventually required. There is no point in evaluation. In addition, in order to achieve the intended improvement in accuracy, it is necessary to fix an automatic wiring tool in a wiring process, and there is a problem that versatility is lacking.

Accordingly, an object of the present invention is to provide a CAD for PCB.
The purpose is to enable the support of the system and the preliminary examination of the design specifications.

[0009]

In order to solve the above-mentioned problems, a printed wiring board design and development support system according to the present invention is provided in a printed circuit board design and development support system for designing a printed circuit board by inputting board specification data. It has a pseudo net list generating means for judging whether or not a net list has been input as a board specification and generating a pseudo net list when the net list has not been input.

A printed wiring board design and development support system according to another aspect of the present invention is a printed circuit board design and development support system for designing a printed circuit board by inputting board specification data and analyzing a pattern distribution density on the printed circuit board. It is displayed as a pattern distribution analysis image, and enables layout design with equalized pattern distribution.

A printed wiring board design and development support system according to still another aspect of the present invention is a printed circuit board design and development support system for designing a printed circuit board by inputting board specification data. The apparatus includes a vacant channel capacity analyzing means, a pattern distribution density analyzing means, a total wiring length analyzing means, and a predictive analyzing means for an average channel use rate.

In the printed wiring board design and development support system of the present invention, as a PCB design and development support, in addition to the average channel usage rate in all layers, the pattern distribution density on the board and the channel usage distribution on the board are visually checked. And output. Also, the sum of the Manhattan line lengths at each pin pair is analyzed as the estimated total wiring length. Further, in order to improve the average channel use accuracy to be analyzed, the channel use ratio analyzed by the CAD system, the channel use ratio after wiring, and an error thereof are registered in a database. During operation, access the error database within this CAD system,
If there is a term corresponding to the analysis channel usage rate, the average value of the error is obtained, and a value obtained by adding the error value to the analysis value is output as the analysis channel usage rate. If there is no applicable section,
The analysis value is output as it is as the analysis channel usage rate.
At the time of output, the analysis source value and the corresponding error average value are also output together with the analysis channel usage rate.

The optimum number of signal layers for a PCB is analyzed based on the length of routable wiring (free channel capacity), the wiring density between pins, and the maximum number of pattern cuts. In addition, a pseudo net list is created based on information such as a mounted component name, a net name, and the number of pins, and the pin coordinates of the pin pair with respect to the PCB are analyzed from the component arrangement position and the mounted component library.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a CAD system for PCB according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a processing flowchart of the PCB CAD system of the present invention. This CAD system for PCB is roughly composed of nine stages.

First, there is a PCB specification input unit 1 for inputting a PCB design specification. FIG. 2 shows an example of the input PCB specification. The input information is held (stored) in the memory.

Next, when there is no pin-to-pin connection information between mounted components in the inputted (or given) PCB specification, the pseudo net list generation unit 2 simulates the correlation between the component and the pin arrangement position. This is to analyze the netlist. This process 2 does not perform the process when the connection information between the mounted components is given as the PCB specification, and gives the given data priority. FIG. 3 shows an example of information necessary for generating the pseudo netlist. A pseudo net list is generated from a component name, a net name, the number of pins, and the like as shown in FIG. 3, and the pin coordinates of the pin pair are analyzed by a mounted component library or the like.

In the third pattern distribution analysis unit 3, as shown in FIG. 4, at least how many patterns pass (or straddle) on a virtual cut line provided on the PCB in parallel with the X axis and the Y axis. Is analyzed from the pin pair information, and the survey cut line coordinates and the number of pattern cuts are registered in respective tables for each of the X axis and the Y axis. Also, the maximum number of pattern cuts is held (stored) in the memory.

Fourth, there is a channel capacity analyzer 4. As shown in the board image of FIG. 5, this is because the free channel capacity (hereinafter referred to as wiring) in the single signal layer (subtracted from the total channel capacity in the PCB) taking into account the prohibited area in the PCB (upper), the area of the mounted components, etc. Is analyzed).

Here, if the number of signal layers is not given as the board (PCB) specification, the processing of the fifth signal layer number analysis unit 5 is performed. Here, the number of wires that can be wired per single signal layer is analyzed by the product of the wiring length per single signal layer and the pattern density analyzed by the fourth channel capacitance analysis unit 4. Here, the value obtained by the quotient of the maximum number of pattern cuts and the number of routable lines per single signal layer is converted into an integer.
The smallest value among the even values larger than the obtained integer value is analyzed as the optimum number of signal layers in the current wiring design.

The sixth is a channel use distribution analyzer 6.
Here, the quotient between the number of pattern cuts analyzed by the third pattern distribution analysis unit 3 and the routable length on the virtually provided cut line is converted into a percentage and analyzed as the channel usage rate on the survey line. The analysis values are separately registered in the table along with the coordinate values of the cut line separately for the X axis and the Y axis.

The seventh is a wiring length analysis. Here, as shown in FIG. 6, based on the connection information between the pins, the line length between the pins is divided into an x-axis component and a y-axis component, and a well-known Manhattan line length whose sum is the line length is obtained. Analyze each pin pair. The sum of the Manhattan wire lengths of all pin pairs is analyzed as the total wire length. The total wiring length obtained here can be referred to as the minimum necessary wiring length in actual design.

Eighth is a channel utilization analysis unit 8. Here, the product of the routable length in a single signal layer and the number of signal layers analyzed by the fourth channel capacitance analysis unit 4 is analyzed as a routable length in all signal layers (hereinafter referred to as a total routable length). . Next, a value obtained by percentage of the quotient of the total wiring length and the total possible wiring length analyzed in the seventh wiring length analysis 7 is analyzed as an average channel utilization rate in all signal totals.

Finally (ninth), the analysis result output unit 9
The number of signal layers, pattern distribution density, channel usage distribution and average channel usage obtained as a result of the analysis are visualized and output. FIG. 6 is an example of this visualization output.

[0025]

As described above, when the PCB CAD system of the present invention is operated, the layout design intended for the wiring design can be performed. In addition, by analyzing the optimal number of signal layers, it is possible to eliminate the return process associated with the change in the number of signal layers after wiring design. The pattern density distribution is clear at a glance, and the pattern distribution can be equalized.

In addition, since the netlist is automatically generated, the number of circuit diagram creation steps is not required. Therefore, P of the present invention
The CAD system for CB can improve the design quality of the PCB and short-circuit the TAT of the design development.

[Brief description of the drawings]

FIG. 1 is a processing flowchart of a preferred embodiment in a PCB CAD system according to the present invention.

FIG. 2 is a diagram illustrating an example of an input board specification according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of pseudo netlist generation necessary data in the embodiment of the present invention.

FIG. 4 is a pattern distribution analysis image diagram in the pattern distribution analysis of FIG. 1;

FIG. 5 is a diagram showing an example of a pattern distribution analysis image of FIG. 1;

FIG. 6 is an image diagram of the wiring length analysis of FIG. 1;

FIG. 7 is a diagram showing an operation example of the CAD system for PCB of the present invention.

FIG. 8 is a diagram showing an output example of the channel use distribution diagram of FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Board specification data 2 Pseudo net list generation unit 3 Pattern distribution analysis unit 4 Channel capacity analysis unit 5 Number of signal layers analysis unit 6 Channel usage distribution analysis unit 7 Wire length analysis unit 8 Channel usage analysis unit 9 Analysis result output unit

Claims (5)

[Claims] In a printed circuit board design development support system for inputting board specification data to design a printed circuit board, it is determined whether or not a netlist has been input as the board specification, and the netlist has not been input. A printed wiring board design and development support system, comprising: a pseudo netlist generating means for generating a pseudo netlist in some cases. 2. A printed wiring board design and development support system for designing a printed circuit board by inputting board specification data, wherein the pattern distribution density on the printed circuit board is analyzed and displayed as a pattern distribution analysis image, and the pattern distribution is equalized. Printed wiring board design and development support system, which enables layout design to be performed. 3. A printed circuit board design and development support system for designing a printed circuit board by inputting board specification data, comprising: an optimum number of signal layers of the printed circuit board; a vacant channel capacity analyzing means; a pattern distribution density analyzing means; A printed wiring board design development support system, comprising: analysis means and means for predicting and analyzing average channel use rate. 4. A step of visualizing and outputting the pattern distribution density on the substrate and the channel usage distribution on the substrate, in addition to the average channel usage rate in all layers, as a PCB design and development support. Analyzing the sum of the Manhattan line lengths as the estimated total wiring length in step 1 and registering the analyzed channel usage rate, the channel usage rate after wiring, and the error in the database in order to improve the average channel usage accuracy to be analyzed Steps and accessing the error database in the system during operation, if there is a term corresponding to the analysis channel usage rate, finds the average value of the errors, and calculates the analysis value plus the error value as the analysis channel usage rate. And outputting the analysis value as it is as the analysis channel utilization rate if there is no corresponding term. A step of analyzing the number of signal layers based on a routable length (vacant channel capacity), a wiring density between pins, and a maximum number of pattern cuts, and a pseudo net list based on information such as a mounted component name, a net name, and the number of pins; Analyzing a pin coordinate of a pin pair with respect to a PCB from a component arrangement position and a mounted component library. 5. The printed wiring board design and development support system according to claim 4, wherein the analysis source value and the corresponding error average value are output together with the analysis channel usage rate.