JP3166847B2 - Recording medium and device recording wiring accommodation evaluation program in printed circuit board design - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium and an apparatus for recording a wiring storability evaluation program in printed circuit board design. The present invention relates to a recording medium and an apparatus for recording a wiring accommodation evaluation program in a printed circuit board design capable of accelerating the evaluation of accommodation.

[0002]

2. Description of the Related Art As a conventional recording medium and apparatus for recording a wiring storability evaluation program in a printed circuit board design, there is one disclosed in Japanese Patent Application Laid-Open No. Hei 9-232722. This means that the number P of wiring pin pairs is calculated from a net list of a logic circuit created in advance, the total number N of wiring channels of the printed board is calculated from predetermined board data input in advance, Wiring accommodating accuracy data K is extracted from the accommodating accuracy data file based on the wiring pin pair number P and the total wiring channel number N, and based on the wiring pin pair number P, the total wiring channel number N, and the wiring accommodating accuracy data K. To judge the wiring accommodability and to easily and surely evaluate in a short time whether or not wiring of a predetermined logic circuit can be accommodated on a printed circuit board having a predetermined number of wiring layers, a wiring grid interval, and a board size. It is.

[0003]

Since the recording medium and the apparatus recording the wiring accommodation evaluation program in the conventional printed circuit board design are configured as described above, the number of pin pairs increases as the density of the printed circuit board increases. Under the current situation (10000 pin pairs or more), the load becomes large in terms of storage capacity and calculation speed, and there is a problem that it takes time to evaluate the wiring accommodation of the printed circuit board. In particular, if you try to evaluate the wiring capacity of various cases by changing the number of layers and recalculating the wiring capacity, changing the board outline, moving components, etc. Has to be redone.

SUMMARY OF THE INVENTION An object of the present invention is to provide a recording medium and an apparatus for recording a wiring accommodation evaluation program in a printed circuit board design capable of speeding up the evaluation of the wiring accommodation of a printed circuit board whose number of pin pairs is increasing due to the increase in density. Is to provide.

[0005]

According to the present invention, a recording medium for recording a wiring storability evaluation program in printed circuit board design according to the present invention stores information on an inputted component and a pin pair which is a connection relation between pins of each component. A component arranging step of arranging the components on the board based on the original, a grouping step of grouping the arranged components based on an arrangement positional relationship and a connection relationship of the components arranged in the component arranging step, A group shape generating step for generating a group shape including the converted parts, and a first wiring accommodating property based on the area of the conductor portion in the group shape generated in the group shape generating step and the area of the group shape. Between a group shape generated in the group shape generating step, A pin pair extracting step of extracting a pin pair between the respective groups to be connected, and passing points of wiring corresponding to the number of pin pairs extracted in the pin pair extracting step are generated on the group shape generated in the group shape generating step. A passing point generating step, a connection information generating step of generating a connection between the passing points generated in the passing point generating step as connection information between groups, and a first wiring accommodation obtained in the intra-group wiring accommodation calculation step. Wiring, based on the characteristics, the area of the conductor portion obtained based on the connection information generated in the connection information generation step, and the area of the entire board on which each group shape generated in the group shape generation step is mounted. The wiring accommodating operation step of obtaining the evaluation information of the wiring accommodability as a numerical value. And characterized by recording a program to be executed in order computer.

A device for evaluating wiring storability in printed circuit board design according to the present invention includes a component list / pin pair information input device for inputting component information and pin pair information indicating a connection relationship of pins of each component. A component arrangement processing unit that arranges components on a board based on the component information input by the pin pair information input device and the pin pair information that is a connection relation of pins of each component, and an arrangement by the component arrangement processing unit A grouping processing unit for grouping the arranged components based on the arrangement positional relationship and the connection relationship of the arranged components; a group shape processing unit for generating a group shape including the components grouped by the grouping processing unit; A group generated by the group shape processing unit when the grouped parts are moved to a state where the connections are short and there are few intersections. A pin pair between the respective groups for connecting the states is extracted, a passing point of the wiring according to the number of the extracted pin pairs is generated on the group shape, and the connection between the generated passing points is set between the groups. And a first numerical value calculated as a numerical value by calculating based on the inter-group connection output unit generated as the connection information, and the area of the conductor portion in the group shape generated by the group shape processing unit and the area of the group shape. Wiring accommodability, based on the area of the conductor between the group shapes obtained based on the connection information generated by the inter-group connection output unit, and the area of the board on which each group shape is placed, based on the A wiring accommodating output section for obtaining the evaluation information of the wiring accommodating property as a numerical value.

According to the present invention, there is provided an apparatus for evaluating wiring storability in a printed circuit board design, comprising:
Based on the first wiring storability obtained by evaluating the evaluation information of the wiring storability inside each group shape as a numerical value, and the wiring storability for each area based on the area of the conductor portion for each area and the area for each area. It is characterized in that the wiring accommodating output unit independently performs the process of obtaining the evaluation information of the sex as a numerical value.

According to the present invention, there is provided a recording medium and an apparatus for recording a wiring storability evaluation program in printed circuit board design,
A plurality of parts are grouped based on the arrangement and connection relationships of the parts, and a group shape including the parts in the group is generated. Calculate based on the area of the board and the area of the board, evaluate the wiring accommodation, change the number of layers to recalculate the wiring accommodation, change the board outline,
It is possible to reduce the time required for evaluating the wiring accommodability of various cases such as moving parts.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. The recording medium and the apparatus storing the wiring storability evaluation program in the printed circuit board design according to the present embodiment arrange components on the board by inputting the connection relation (pin pair) between the components and the pins of each component, and arrange the components on the substrate. A plurality of parts are grouped based on the relationship and the connection relation, a group shape including parts in the group is generated, a pin pair connected to another group is extracted from a certain group, and the number of the pin pairs on the group shape is equal to the number of the pin pairs. Generates a passing point (passing pin) of the wiring, generates the connection between the virtual pins as connection information between the groups, and stores the wiring capacity within each group and between the groups (the area of a conductor portion such as a pin or a wiring). And expressed by the ratio of the outer shape area of the substrate) to evaluate the wiring accommodating property. Further, the calculation of the wiring storability is performed in parallel for each group.

FIG. 1 is a block diagram showing a configuration of an apparatus for evaluating wiring accommodability in designing a printed circuit board according to the present embodiment. The evaluation device includes an input device 1 such as a keyboard and a mouse, a data processing device 2 operated by program control, a storage device 3 for storing information, an output device 4 such as a display device and a printing device, a component list A pin pair information input device 5 and the like are provided.

The data processing device 2 includes a component placement processing unit 2
1, grouping processing unit 22, group shape processing unit 23,
Group connection output section 24 and wiring accommodation output section 2
5 and the like.

The component arrangement processing section 21 performs processing for manually arranging components on a board based on information in the component list / pin pair information storage section 31. FIG. 3 shows an image in which components are arranged by the component arrangement processing unit 21.

The grouping processing unit 22 performs processing for manually grouping the components arranged by the component arrangement processing unit 21 in consideration of the positional relationship and the connection relationship of the pin pairs.

The group shape processing section 23 automatically generates a rectangle on the grid including the grouped parts and the wiring area between the parts. FIG. 4 shows an image when the parts are grouped by the group shape processing unit 23. In FIG. 4, P1 to P3 represent components, and dotted lines represent wiring regions. A rectangular shape G1 including these
Is a group shape. Regarding a method of calculating the wiring area (dotted line portion in FIG. 4) inside this group, a path for obtaining a Manhattan length (length in the X-axis direction + length in the Y-axis direction) connecting the pin pairs (hereinafter referred to as a path of the Manhattan length) ) And a line width (obtained from the board information storage unit 34) are used as a wiring area.

The intergroup connection output section 24 determines where and where the virtual pins of the group must be wired, and stores the information (virtual pin pairs) in the intergroup connection storage section 33. . The virtual pin connected between the groups is a virtual passing point on the group shape G through which the wiring passes. In the method of calculating the virtual pins, a pin pair connecting between groups is extracted, and x1, x2, and x3 indicated by circles in FIG. 4 which are intersections of the calculated Manhattan length path and the group shape G are obtained. FIG. 5 shows an image of the result of calculating the virtual pins of the entire substrate. As a result of calculating the virtual pins, if the virtual pins overlap, the position of the virtual pins is moved in accordance with the grid so as not to overlap. In addition, when virtual pins are generated in accordance with the rule that does not overlap and the virtual pins do not fit in the group shape, that is, when the virtual pins are completely filled on the group shape, the vertical and horizontal directions of the group shape are used. The length is increased by a multiple of the grid width to increase the group shape so that the virtual pins do not overlap the group shape.

The wiring accommodating output section 25 obtains the wiring accommodating value as a numerical value by the ratio of the area of the conductor portion to the entire area. In the present embodiment, the wiring accommodating output section 25 outputs two kinds of wiring accommodating characteristics. First, as shown in FIG. 4, the case where the wiring storability inside the group is obtained is determined by combining the area of the pin shape and the wiring area inside the group, that is, the area of the conductor portion, the area of the group shape, That is, the ratio to the total area in the group is calculated, and the result is output to the wiring accommodation storage unit 35. In this calculation, since the pin shape area is added or the wiring area of the pin pair is calculated, a processing time corresponding to the number of pin pairs in each group is required.

The second is a case in which the wiring accommodating property of the whole substrate is obtained. First, the area of each group is determined by GS1, GS2,
.. GSn, and the wiring storability calculated for each group is GA1, GA2,. With this value, the conductor area inside each group is obtained by GA1 × GS1. A wiring area between groups (between virtual pins)
S, when the board outer area is BS, the wiring accommodating property of the entire board is the sum of the conductor areas of each group (GA1 × GS1) +
The area of the sum of (GA2 × GS2) +... + (GAn × GSn) and the wiring area AS between the groups is the board outer area BS.
ＧＡ (GA1 × GS1) + (G
A2 × GS2) +... + (GAn × GSn) + AS｝
/ BS.

This calculation requires a processing time corresponding to the number of virtual pin pairs to obtain the wiring area AS between groups. In the case of a multi-layer substrate, the area of the first group shape and the area of the second substrate can be wired as many as the number of layers.

The storage device 3 includes a parts list / pin pair information storage unit 31, a group area storage unit 32, an inter-group connection storage unit 33, a board information storage unit 34, and a wiring accommodation storage unit 35.

The parts list / pin pair information storage section 31
A list of components to be arranged, a list of pin pairs to be wired, and shapes of components and shapes and positions of component pins are stored. The group area storage unit 32 stores the shapes when the components are arranged and then grouped.

The inter-group connection storage unit 33 stores information such as which virtual pins need to be wired.

The board information storage unit 34 stores the shape of the printed board, the number of layers, the line width when wiring is actually performed, and the clearance (for example, how much space is placed between objects such as component pins, etc.) at the time of arrangement and wiring. The value of the gap)
And grids (points at which component pins are placed on the board or points at which wiring passes).

The wiring accommodating storage unit 35 stores a numerical value of the wiring accommodating calculated in each group.

The parts list / pin pair information input device 5
A device that inputs (or reads from an external storage medium) a component to be placed on a board, pin pair information indicating a connection relationship between the component pins, and a component shape and a pin shape / position (that is, a library of components). Then, the input information is stored in the parts list / pin pair information storage unit 31.

Next, the operation will be described. FIG. 2 is a flowchart showing the operation of the evaluation apparatus for wiring accommodation in the printed circuit board design according to the present embodiment. First, component list / pin pair information is input (step A0), components are arranged on a board based on the information (step A1, component placement step), and components are grouped (step A0).
(2, grouping step, group shape generation step), and the processing from step A1 to step A2 is repeated (step A3). FIG. 3 shows an image when the components are arranged. P1 to P7 represent parts, and the dotted lines are Manhattan-length paths output based on the pin pair information.

FIG. 5 shows an image obtained when these are grouped. In the grouping method, a grouping process is performed by manually selecting a plurality of components while observing the positional relationship between the components and the connection relationship between the pin pairs. G1 to G3 in FIG. 5 represent groups, and dotted lines represent connection information between groups. The group G1 has a rectangular group shape shown in FIG. 4 that includes the components P1, P2, P3 and their wiring regions in FIG. Similarly, G2 is a group shape when the components P4 and P5 are grouped, and G3 is a group shape when the components P6 and P7 are grouped.

A circle x in FIG. 5 is a virtual pin connecting the group shapes. This virtual pin is, as shown by the round point in FIG. 4, an intersection of the path of the Manhattan length of the pin pair connected between the groups and the group shape, and a point generated so that the virtual pins do not overlap. These group shapes are stored in the group area storage unit 32, and the connection information is stored in the inter-group connection storage unit 33.

Thereafter, the part group is manually moved,
The connection between groups is made as short as possible and the number of intersections is reduced so that the wiring accommodating property is improved (step A).
4). When the number of layers and the outer shape of the substrate are input (changed), the operations are performed and stored in the substrate information storage unit 35 (step A5).

If the wiring storability inside each group is not calculated, the calculation inside the group is performed. Note that this calculation method uses the first calculation method described above performed in the wiring accommodation output section 25. And
The output is output to the wiring accommodating storage unit 35, and finally, the wiring accommodating ability of the entire board is obtained. Note that this calculation method uses the second calculation method described above, which is performed by the wiring accommodation output unit 25. Then, the result is output to the output device 4 (step A6, intra-group wiring accommodation calculation step, pin pair extraction step, pass point generation step, connection information generation step, wiring accommodation calculation step).

Since the wiring storability obtained as described above is an area ratio, it is output as a numerical value such as 0.22. This is an index indicating the accommodability of the wiring, and the smaller the value, the wider the area for wiring can be taken, which means that the wiring is easier.
In addition, since the pin pairs are independent for the calculation of the wiring accommodating property of each group, it can be processed in parallel by another process or another computer. When recalculating this value by changing the number of layers or when changing the shape of the substrate (step A7), it is possible to start over from step A5 again. Also, when the part group is moved (step A8), the process can be repeated from step 4. In either case, since the wiring accommodating property within the group has already been calculated, it is possible to perform only the calculation between the groups, that is, only the processing by the second calculating method in the wiring accommodating output unit 25.

As described above, according to this embodiment, the speed of the interactive operation can be increased. In other words, when designing a printed circuit board, the evaluation of the wiring accommodating property is repeatedly performed by trial and error to evaluate how to arrange the components to make the wiring easier. Since the wiring accommodating capacity does not change, it is sufficient to calculate only the wiring accommodating capacity between groups. For example, in the example of FIG.
However, since there are only four virtual pin pairs, when a group is moved and repeated calculations are performed, processing for four pins is sufficient, and as a result, there is an effect that the repetition processing can be sped up.

Further, according to the present embodiment, by grouping the components, the region on the board is divided, and the calculation of the wiring accommodation between groups and within each group can be performed independently. Therefore, by performing these individual calculations in parallel by another process or another computer, there is an effect that the calculation of the wiring accommodation of the entire board can be performed in a short time.

Next, another embodiment of the present invention will be described. FIG. 6 is a block diagram showing a configuration of a wiring accommodation evaluation apparatus in designing a printed circuit board according to the present embodiment. 6, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The evaluation device includes a recording medium 6 on which a data processing program is recorded. This recording medium 6 may be a magnetic disk, a semiconductor memory, or another recording medium. The data processing program includes:
This is a program for realizing the evaluation of the wiring storability in the printed circuit board design described in the embodiment by the data processing device 7, and is recorded on the recording medium 6. The data processing program is read from the recording medium 6 into the data processing device 7 and controls the operation of the data processing device 7.
The data processing device 7 executes the same processing as that of the data processing device 2 shown in FIG. 1 in the embodiment under the control of the data processing program. As described above, also in the present embodiment, the same effects as in the above-described embodiment can be obtained.

Next, another embodiment of the present invention will be described. Although the component placement processing unit 21 in FIG. 1 described in the above embodiment manually places the component P, in the present embodiment, the component P is automatically placed so that the component P does not overlap from the end of the board. . That is, in step A1 in FIG. 2, the state in which the parts shown in FIG. 3 are arranged is automatically created based on the part shape and the clearance, and then the parts are moved as intended by the user. As described above, in the present embodiment, the basic processing for component placement performed by the component placement processing unit 21 can be automated, the functionality is improved, and the same effects as in the above-described embodiment can be obtained.

[0035]

According to the present invention, a plurality of parts are grouped based on the arrangement positional relation and the connection relation of the parts, and a group shape including the parts in the group is generated. Calculate the wiring capacity as a numerical value based on the area of the conductor part such as pins and wiring and the board area
Since the configuration is designed to evaluate the wiring accommodability, the wiring accommodating ability of various cases when changing the number of layers to recalculate the wiring accommodating ability, changing the outer shape of the board, or moving components, etc. The evaluation can be performed for each of the group shapes and for each set of the group shapes, so that it is easy to use the wiring accommodating property for each of the group shapes already determined, and for each of the group shapes and the set of the group shapes. It is easy to perform the evaluation of the wiring accommodability in each case, and the time required for the evaluation of the wiring accommodating accompanying the change in the number of layers, the change in the outer shape of the board, the movement of components, and the like can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a wiring accommodation evaluation apparatus in a printed circuit board design according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the evaluation apparatus for wiring storability in designing a printed circuit board according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an image when a component is arranged on a board in the apparatus for evaluating wiring storability in printed circuit board design according to one embodiment of the present invention;

FIG. 4 is an explanatory diagram showing an image when components are grouped by a group shape processing unit in the apparatus for evaluating wiring storability in printed circuit board design according to one embodiment of the present invention;

FIG. 5 is an explanatory diagram showing an image when the components are grouped in the evaluation apparatus for wiring storability in printed circuit board design according to one embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a wiring accommodation evaluation apparatus in a printed circuit board design according to another embodiment of the present invention.

[Explanation of symbols]

5: component list / pin pair information recording unit, 21: component placement processing unit, 22: grouping processing unit, 23: group shape processing unit, 24: inter-group connection output unit, 25
... Wiring accommodating output unit, step A1 (part placement step), step A2 (grouping step, group shape generating step), step A6 (wiring accommodating intra-group calculating step, pin pair extracting step, passing point generating step, connection) Information generation step, wiring accommodation calculation step).

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-106478 (JP, A) JP-A-5-233762 (JP, A) JP-A-4-167181 (JP, A) JP-A-9-99 198427 (JP, A) JP-A-9-62731 (JP, A) JP-A-7-56982 (JP, A) Fixed and profitable, 3 outsiders, "Arrangement for large-scale gate arrays to reduce wiring congestion Improvement Method ", Information Processing Society of Japan Research Report (DA-84), Information Processing Society of Japan, May 1997, Vol. 97, no. 50, p. 29-26 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 666 JICST file (JOIS)

Claims (3)

(57) [Claims] 1. Connection between input components and pins of each component
On the board based on information about the pin pair
A component placement step for placing the component, and a contact position relationship between the components placed in the component placement step;
Group that groups the placed parts based on the connection relationship
Including the grouping step and the parts grouped in the grouping step
A group shape generating step for generating a group shape, and a group shape generated in the group shape generating step.
Based on the area of the conductor part and the area of the group shape
Finding the first wiring capacity as a numerical value
A capacity calculation step; and a group shape generated in the group shape generation step.
Extract pin pairs between each group that connect between
A pin pair extracting step and a group shape generated in the group shape generating step
Above, the pin pair extracted in the pin pair extraction step
Passing point generation step for generating passing points of wiring according to the number
And the connection between the passing points generated in the passing point generation step.
Connection information generation step to generate connection information between groups
And the first calculated in the intra-group wiring accommodation calculation step.
Wiring accommodability and the connection generated in the connection information generation step
The area of the conductor part obtained based on the line information and the glue
The base on which each group shape generated in the
Based on the total area of the board, the numerical value
The wiring accommodating calculation step required as a wiring accommodating evaluation program in printed circuit board design
A computer readable recording medium recorded as a computer. 2. The component information and the connection relation of the pins of each component.
Parts list and pin pair information to input certain pin pair information
The input device and the component list / pin pair information input device
The pin information, which is the connection relationship between the component information and the pin of each component,
Component placement to place components on the board based on the
Processing part, and the arrangement positional relationship of the parts arranged by the part arrangement processing part.
A group that groups the placed components based on the connection relationship
Grouping unit and the parts grouped by the grouping unit.
A group shape processing unit that generates a group shape that is different from the group shape in a state where the connections between groups are short and there are few intersections
The group shape when the looped parts are moved
To connect between the group shapes generated in the shape processing unit.
Extract pin pairs between groups, and
The passing points of the wiring according to the number of the extracted pin pairs are
Generate the connections between the generated passing points and connect the groups
An inter-group connection output unit generated as information, and a group shape generated by the group shape processing unit .
Based on the area of the conductor part and the area of the group shape
The first wiring accommodating property calculated as a numerical value and the
Acquired based on the connection information generated by the loop connection output section
Area of the conductor portion between the group shapes
Based on the area of the board on which the shape is mounted,
Put it comprises a wiring capacity output unit for obtaining the evaluation information sex as a numerical value, to a printed circuit board design, wherein
Evaluation device for wiring capacity. 3. The wiring accommodating output section includes a divided base.
Evaluation of wiring capacity inside each group shape for each area on the board
The first wiring accommodating property for which price information was obtained as a numerical value,
Based on the area of the conductor portion for each area and the area of each area,
Obtain evaluation information of wiring storability for each area as a numerical value
3. The process according to claim 2, wherein the processes are performed independently.
Evaluation equipment for wiring accommodability in lint board design.