JP3662722B2 - Printed circuit board design and development support method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board design development support method (hereinafter simply referred to as a CAD method for PCB).
[0002]
[Prior art]
Advances in semiconductor technology, particularly semiconductor integrated circuit (IC) technology, have applied electronics technology to most devices. This electronic circuit is generally configured by arranging various active and passive electronic components on a printed wiring board (PCB or PWB) and soldering them.
[0003]
As electronic application devices become more sophisticated, PCB design becomes more and more complex, and it takes time and effort for the designer to design manually, and the designed PCB is designed to operate normally without causing problems. It is very difficult to do. Therefore, it is usual to use a CAD system for PCB, and to design a PCB efficiently and with high quality in cooperation with an operator (designer) using various data stored in the system.
[0004]
As a conventional example of such a CAD system for PCB, there is JP-A-4-111400. This publication discloses a printed circuit board component placement evaluation method, and in order to analyze a highly accurate evaluation value (expected value of temporary wiring length), information on the temporary wiring path considering the characteristics of the actual wiring algorithm is pre-wiring information. Judge more.
[0005]
According to this prior art, a channel that cannot be routed is read from the board information and registered in a table holding empty channel information. In addition, a flag indicating that it is directly under the part is set, the part directly under the part is counted for each divided area, and the other free channels are counted, and the wiring possibility directly under the part and the wiring frequency coefficient for each layer are input from the board information. Then, the total length of the free channels in the divided area is totaled for each path.
[0006]
[Problems to be solved by the invention]
The prior art described above has the following problems or problems to be solved.
First, since the channel usage rate in all layers is output as numerical value data only as an evaluation value of the pattern congestion level, it is impossible to recognize where the pattern is concentrated on the printed circuit board. For this reason, it cannot be reflected in the wiring design. In other words, there is a drawback that it is only possible to evaluate the quality of the current specific arrangement, and does not support the rearrangement design for equalizing the pattern distribution.
[0007]
Next, since temporary wiring is specified in consideration of the characteristics of the actual wiring algorithm, processing turnaround time (TAT) equivalent to automatic wiring is required after all, meaning the evaluation of component placement before wiring There is no. In addition, in order to achieve the desired accuracy improvement, it is necessary to fix an automatic wiring tool in the wiring processing, and there is a problem that the versatility is lacking.
[0008]
Accordingly, an object of the present invention is to enable support of a CAD system for PCB and advance examination of design specifications.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems, a printed circuit board design / development support system according to the present invention is a printed circuit board design / development support system for designing a printed circuit board by inputting board specification data including pin pair information of mounted components. Pattern distribution analysis means for analyzing, based on the pin pair information, at least how many patterns pass or straddle on a virtual cut line provided parallel to the X-axis and Y-axis, and prohibition on the printed circuit board A channel capacity analyzing means for analyzing an empty channel capacity indicating a wireable length in a single signal layer in consideration of a region and a mounted component area, and the channel capacity analyzing step when the number of signal layers is not given as the board specification data The number of wires that can be wired per single signal layer is analyzed by the product of the wiring length per single signal layer and the pattern density analyzed in Optimum in the current wiring design, the smallest value among the even values larger than the integer value obtained by converting the value obtained by dividing the number of large pattern cuts and the number of wires that can be wired per single signal layer into an integer The quotient of the signal layer number analyzing means for analyzing the number of signal layers, the number of pattern cuts analyzed in the pattern distribution analysis step, and the possible wiring length on the virtually provided cut line is expressed as a percentage. Based on the channel usage distribution analyzing means for analyzing the channel usage rate and the inter-pin connection information, the line length between the pins is divided into the x-axis component and the y-axis component, and the sum of the components is defined as the line length. Analyzing the Manhattan line length for each pin pair, wiring length analysis means for analyzing the total Manhattan line length of all pin pairs as the total wiring length, and wiring in a single signal layer analyzed in the channel capacity analysis step Possible And the number of signal layers is analyzed as the wiring length in all signal layers, and the value obtained by dividing the quotient of the total wiring length and the total wiring length analyzed in the wiring length analysis step as an average in all signals Channel usage rate analyzing means for analyzing as channel usage rate, and analysis result output means for visualizing and outputting the number of signal layers, pattern distribution density, channel usage distribution and average channel usage rate obtained as a result of the analysis. .
[0010]
The printed circuit board design and development support system according to another aspect of the present invention provides a pattern development density on the printed circuit board and channel use on the board in addition to the average channel usage rate in all layers as the design development support of the printed circuit board. Means for visualizing and outputting the distribution, means for analyzing the sum of Manhattan line lengths for each pin pair as the predicted total wiring length, and analyzing the channel usage rate and wiring to improve the average channel usage accuracy to be analyzed Means to register the channel usage rate and its error in the database later, and access the error database in the system at the time of operation, and if there is a term corresponding to the analysis channel usage rate, find the average value of the error and analyze it The value plus the error value is output as the analysis channel usage rate. If there is no applicable term, the analysis value is used as is. A means for outputting the data as a utilization rate, a means for analyzing the optimal number of signal layers for the printed circuit board by the wiring length (free channel capacity), the wiring density between pins and the maximum number of pattern cuts, the name of the mounted component, the net name, A pseudo net list is created based on the information on the number of pins, and includes means for analyzing pin coordinates of a pin pair with respect to the printed circuit board from a component placement position and a mounted component library. Here, the analysis source value and the corresponding error average value are also output together with the analysis channel usage rate.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the CAD method for PCB of the present invention will be described in detail with reference to the accompanying drawings.
[0015]
FIG. 1 shows a processing flowchart of the CAD method for PCB of the present invention. This PCB CAD method is roughly divided into nine stages.
[0016]
First, there is a PCB specification input unit 1 for inputting a PCB design specification. An example of this input PCB specification is shown in FIG. Each input information is held (stored) in a memory.
[0017]
Next, when there is no inter-pin connection information between mounted components in the input (or given) PCB specification, the pseudo net list generation unit 2 displays the pseudo net list in the correlation such as the component-pin arrangement position. To analyze. In the process 2, when the inter-pin connection information between the mounted components is given as the PCB specification, the process is not performed and the given data is given priority. An example of information necessary for generating the pseudo netlist is shown in FIG. A pseudo net list is generated from the part name, net name, number of pins, etc. as shown in FIG. 3, and the pin coordinates of the pin pair are analyzed by the mounted part library.
[0018]
In the third pattern distribution analysis unit 3, as shown in FIG. 4, the minimum number of patterns that pass (or straddle) on a virtual cut line provided in parallel with the X axis and the Y axis on the PCB is pinned. The analysis is performed based on the pair information, and the investigation cut line coordinates and the number of pattern cuts are registered in the respective tables for each X axis and Y axis. The maximum number of pattern cuts is held (stored) in the memory.
[0019]
Fourth, there is a channel capacity analysis unit 4. This is because, as shown in the substrate image of FIG. 5, the empty channel capacity (hereinafter referred to as wiring) in a single signal layer is considered (subtracted from the total channel capacity in the PCB) in consideration of the prohibited area in the PCB (upper), the mounting component area, and the like. Analyze possible length).
[0020]
Here, when the number of signal layers is not given as the substrate (PCB) specification, the fifth signal layer number analysis unit 5 performs processing. Here, the number of wires that can be wired per single signal layer is analyzed based on the product of the wire length per single signal layer and the pattern density analyzed by the fourth channel capacity analysis unit 4. Here, the value obtained by the quotient of the maximum number of pattern cuts and the number of wires that can be wired per single signal layer is converted into an integer. The smallest value among the even numbers larger than the obtained integer value is analyzed as the optimum number of signal layers in the current wiring design.
[0021]
The sixth is the channel usage distribution analysis unit 6. Here, the quotient of the number of pattern cuts analyzed by the third pattern distribution analysis unit 3 and the wireable length on the virtually provided cut line is converted into a percentage and analyzed as the channel usage rate on the survey line. This analysis value is registered in the table together with the coordinate value of the cut line separately for each of the X axis and the Y axis.
[0022]
The seventh is wiring length analysis. Here, as shown in FIG. 6, based on the connection information between pins, the line length between pins is divided into an x-axis component and a y-axis component, and a known Manhattan line length with the sum of the components as the line length is obtained. Analyze for each pin pair. The total sum of Manhattan wire lengths for all pin pairs is analyzed as the total wire length. The total wiring length obtained here can be referred to as the minimum wiring length necessary in actual design.
[0023]
The eighth is the channel usage rate analysis unit 8. Here, the product of the routable length in the single signal layer and the number of signal layers analyzed by the fourth channel capacity analyzing unit 4 is analyzed as the routable length in all signal layers (hereinafter referred to as the total routable length). . Next, a value obtained by dividing the quotient of the total wiring length and the total wiring possible length analyzed in the seventh wiring length analysis 7 is analyzed as an average channel usage rate in all signals.
[0024]
Finally (9th), the analysis result output unit 9 visualizes and outputs the number of signal layers, the pattern distribution density, the channel usage distribution, and the average channel usage rate obtained as a result of the analysis. FIG. 6 is an example of this visualization output.
[0025]
【The invention's effect】
As described above, when the PCB CAD method of the present invention is used, layout design intended for wiring design becomes possible. Further, by analyzing the optimal number of signal layers, it is possible to eliminate the backtracking process associated with the change in the number of signal layers after the wiring design. The pattern density distribution is obvious and the pattern distribution can be equalized.
[0026]
Further, since the net list is automatically generated, the circuit diagram creation man-hour is not required. Therefore, the PCB CAD method of the present invention makes it possible to improve the design quality of the PCB and to short-circuit the TAT for design development.
[Brief description of the drawings]
FIG. 1 is a process flowchart of a preferred embodiment of a CAD method for PCB according to the present invention.
FIG. 2 is a diagram showing an example of an input board specification in the embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of pseudo net list generation necessary data according to the embodiment of the present invention.
4 is a pattern distribution analysis image diagram in the pattern distribution analysis of FIG. 1. FIG.
5 is a diagram showing an example of a pattern distribution analysis image of FIG. 1. FIG.
6 is a wiring length analysis image diagram of FIG. 1. FIG.
FIG. 7 is a diagram showing an operation example of the CAD method for PCB according to the present invention.
8 is a diagram showing an output example of the channel usage distribution chart of FIG. 1. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Board specification data 2 Pseudo net list generation part 3 Pattern distribution analysis part 4 Channel capacity analysis part 5 Signal layer number analysis part 6 Channel use distribution analysis part 7 Wire length analysis part 8 Channel usage rate analysis part 9 Analysis result output part

Claims (3)

In a printed circuit board design development support system that designs printed circuit boards by inputting board specification data including pin pair information of mounted components,
Pattern distribution analysis means for analyzing, based on the pin pair information, how many patterns pass or straddle on a virtual cut line provided parallel to the X axis and the Y axis on the printed circuit board;
A channel capacity analyzing means for analyzing a vacant channel capacity indicating a routable length in a single signal layer in consideration of a prohibited area on the printed circuit board and a mounting component area;
When the number of signal layers is not given as the board specification data, the number of wires that can be wired per single signal layer is obtained by multiplying the wiring density per single signal layer analyzed in the channel capacity analysis step by the pattern density. And the smallest value among the even values larger than the integer value obtained by converting the value obtained from the quotient of the maximum number of pattern cuts and the number of wires that can be wired per single signal layer to an integer. Signal layer number analysis means for analyzing the optimum number of signal layers in the design,
Channel usage distribution analysis means for analyzing the percentage of quotients of the number of pattern cuts analyzed in the pattern distribution analysis step and the possible wiring length on the virtually provided cut line as a channel usage rate on the survey line;
Based on the inter-pin connection information, the line length between the pins is divided into an x-axis component and a y-axis component, and the Manhattan line length with the sum of the components as the line length is analyzed for each pin pair. Wire length analysis means for analyzing the sum of the Manhattan wire lengths of pin pairs as the total wire length,
The product of the routable length in the single signal layer analyzed in the channel capacity analysis step and the number of signal layers is analyzed as the routable length in all signal layers, and the total wiring length and total wiring analyzed in the wiring length analysis step A channel usage analysis means for analyzing a value obtained by dividing the quotient of the possible length as a percentage as an average channel usage in the total of all signals;
An analysis result output means for visualizing and outputting the number of signal layers, pattern distribution density, channel usage distribution and average channel usage rate obtained as a result of the analysis;
A printed wiring board design development support system characterized by comprising: As a design development support of the printed circuit board, in addition to the average channel usage rate in all layers, means for visualizing and outputting the distribution density of the pattern on the printed circuit board and the channel usage distribution on the circuit board,
Means for analyzing the total Manhattan line length in each pin pair as the predicted total wiring length;
In order to improve the average channel usage accuracy to be analyzed, means for registering the analyzed channel usage rate, the channel usage rate after wiring and its error in a database,
During operation, access the error database in the system, and if there is a term corresponding to the analysis channel usage rate, calculate the average value of the error and output the analysis value plus the error value as the analysis channel usage rate. If there is no corresponding term, means for outputting the analysis value as the analysis channel usage rate,
A means for analyzing the optimal number of signal layers for the printed circuit board by wiring length (free channel capacity), wiring density between pins, and maximum number of pattern cuts;
A means for creating a pseudo net list based on information on the mounted component name, net name, and pin count, and analyzing the pin coordinates of the pin pair for the printed circuit board from the component placement position and the mounted component library;
A printed circuit board design development support system characterized by comprising:   The printed circuit board design and development support system according to claim 2, wherein the analysis source value and the corresponding error average value are also output together with the analysis channel usage rate.

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