JP3027962B2 - Wiring capacity evaluation method and wiring capacity evaluation system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a printed circuit board.
The present invention relates to a method and a system for evaluating wiring accommodability when designing a wiring pattern by arranging components such as C and a resistor.

[0002]

2. Description of the Related Art Conventionally, in the design of a printed circuit board, a method of interactively arranging components such as an IC and a resistor on a board by a graphic display and designing a wiring pattern has been used. Wiring patterns were designed. As an automatic wiring method for a printed circuit board, for example, Japanese Patent Application Laid-Open No. 63-272094 discloses a method of repeating the operation of determining a wiring between two points on grid points regularly arranged on a printed circuit board. In the method, the printed circuit board is divided into a plurality of small areas including a plurality of grid points, and a schematic wiring for searching and registering wirings between the respective small areas is performed. An automatic wiring method for performing detailed wiring for determining wiring is disclosed.

[0003] Regarding the wiring accommodating property of a printed circuit board, for example, even with the same printed circuit board, the wiring ratio differs depending on the skill of the person who designs the wiring pattern, and the automatic wiring tool (router) also varies depending on the algorithm of each CAD vendor. Since the wiring ratio is different, it cannot be easily evaluated from known parameters such as the substrate size, design criteria (line width, conductor spacing, via diameter, etc.), and the number of layers. Therefore, in general, estimation is performed using a statistical method based on past data (for example, an approximate expression derived from statistical data). For example, in a printed circuit board designed in the past, the wiring storability based on the relationship between the type of component and the number of layers has been examined and statistically evaluated.

[0004]

In the case of designing a wiring pattern by arranging components such as ICs on a printed circuit board, it is necessary to evaluate the wiring accommodating ability from a rough circuit configuration image before deciding the details of the circuit. In some cases, the wiring cannot be accommodated at the stage of forming the wiring pattern, and in such a case, much time is required for the correction. This problem becomes remarkable especially when a large-scale printed circuit is manufactured. For this reason, it is necessary to evaluate the wiring accommodating ability from a rough circuit configuration image before determining the details of the circuit in order to efficiently design the printed circuit board.

In the evaluation of the wiring accommodability by the conventional statistical method, it is only necessary that conditions such as the type of components, the number of layers of the printed circuit board, and the mounting method match the past statistical data.
If the conditions do not match, it is not possible to evaluate the wiring accommodation. Therefore, it is not suitable for evaluating the wiring accommodating ability from a rough circuit configuration image.

The automatic wiring tool is intended to generate a final wiring pattern. Since the automatic wiring tool does not operate without detailed information such as coordinate information to be connected, a wiring width that can be generated, and a wiring interval, such information is not available. Until it is determined, it is not possible to evaluate the wiring accommodation, and it is not possible to evaluate the wiring accommodation before determining the details of the circuit. In addition, since it takes time to generate a wiring pattern having no problem with the intersection of the wiring patterns and the design rules, it takes a lot of time to generate the wiring pattern, and it is necessary to easily evaluate the wiring storability. Can not.

It is an object of the present invention to determine the circuit accommodating ability from a rough image of a circuit configuration using parameters such as a board size, a design standard (line width, conductor spacing, via diameter, etc.) and the number of layers before determining the details of the circuit. It is an object of the present invention to provide a method and a system capable of easily evaluating the system.

[0008]

In order to achieve the above object, a method for evaluating wiring accommodation of the present invention is a method for evaluating wiring accommodation when designing a wiring pattern by arranging components on a printed circuit board. A first step of defining the number of pins and a pin type of a component arranged on the printed circuit board; a second step of defining the size and the number of layers of the printed circuit board; A third step of defining an interval, a via-hole diameter, and a through-hole diameter; and reducing the number of virtual pin pairs that can be paired between components arranged on the printed circuit board to one half of the sum of the pins of both components. And the length of the virtual wiring connecting between the pins of the virtual pin pair is set to 2 of the longest path obtained from the vertical and horizontal sizes of the printed circuit board.
Calculating a channel area per layer by dividing the vertical and horizontal sizes of the printed circuit board by the intervals of the wiring patterns, respectively;
A sixth step of calculating the total channel area of the printed circuit board by multiplying the number of layers by the number of layers, and when the pin type of the component is surface mounting, the number of pairs at a predetermined ratio of the number of virtual pin pairs is determined by the number of via holes. Calculate the channel area occupied by each pin of the virtual wiring and both parts and the channel area occupied by the via hole in each layer, and use the sum as the occupied channel area, and when the pin type of the part is through-hole mounting Calculates the channel area occupied by the virtual wiring and the channel area occupied by the through-holes corresponding to the pins of the two components in each layer, and determines the sum thereof as the occupied channel area. The method is characterized in that the method includes a seventh step of calculating the ratio of the occupied channel area to evaluate the wiring accommodating property.

In the above case, the total channel area and the occupied channel area calculated in the seventh step are divided into lattice units to obtain the total channel number and the occupied channel number. The wiring accommodating property may be evaluated by calculating the ratio.

[0010] The definitions performed in the first to third steps may be interactively performed by a graphic display.

A wiring accommodation evaluation system according to the present invention is a system for evaluating wiring accommodation when designing a wiring pattern by arranging components on a printed circuit board. Component information defining means for defining the number of pins as component information; board shape defining means for defining the size and the number of layers of the printed board as board shape information; width and interval of the wiring pattern, and via hole diameter as board information. The board information defining means to be defined and the number of virtual pin pairs that can be paired between the components arranged on the printed board, the average length of the virtual wiring connecting the pins of the virtual pin pair, and the number of via holes, respectively. Calculating formula defining means for defining a calculating formula to be calculated; and arranging the component information, board outer shape information, and board information on a printed circuit board using the calculating formula. Virtual pin pair number between the parts to be, wire length, calculates the number of via holes, to calculate the channel area occupied by the wirings on the basis of the calculated output result,
A wiring accommodating calculating means for calculating the total channel area of the printed circuit board and calculating the wiring accommodating ability from the ratio of the occupied channel area to the total channel area.

Further , the wiring accommodation evaluation system of the present invention.
Place components on the printed circuit board and set the wiring pattern.
This is a system that evaluates the wiring storability when measuring
Information on the number of pins of components placed on the printed circuit board
Component information defining means defined as
Board that defines the size and number of layers as board outline information
Outer shape defining means, and the width, spacing, and spacing of the wiring pattern;
A board information definition method that defines the through hole diameter as board information
And a pair between the components and the components arranged on the printed circuit board.
Number of virtual pin pairs that can be
Average length of virtual wiring connecting pins, through-holes occupy
Formula to define the formula to calculate each area
Definition means and whether the component information, board outline information, board information
Based on the result calculated using the above calculation formula.
Calculate the occupied channel area and
Calculate the total channel area of the
The wiring accommodating capacity from the ratio of the occupied channel area
And a wiring accommodation raw calculation means .

In any of the above systems, the component
Components defined by the information definition means are defined by the board outline definition means
Having a component arranging means for arranging on the outer shape of the board
May be. Furthermore, component information definition means, board outline definition
Means, board information defining means, and component arranging means,
The input and the component arrangement may be performed interactively.
Further, the apparatus further comprises a grid defining means for defining a size of the grid, wherein the wiring accommodation raw calculation means divides the total channel area and the occupied channel area into grid units defined by the grid defining means, respectively. The number of occupied channels and the number of occupied channels may be obtained, and the wiring accommodating capacity may be calculated from the ratio of the number of occupied channels to the total number of channels.

<Operation> In the present invention, the number of pins and pin types of components arranged on a printed circuit board, the size and the number of layers of a printed circuit board, the width and interval of a wiring pattern, the diameter of a via hole, and the diameter of a through hole are parameters. Since it is possible to evaluate the wiring storability in various combinations of components, it is possible to easily evaluate the wiring storability from a rough circuit configuration image.

In addition, since the wiring accommodating property can be evaluated without generating a detailed wiring pattern, there is no problem that it takes a lot of time to generate a wiring pattern.

In the method of the present invention, in which the number of virtual pin pairs is set to one half of the sum of the pins and the length of the virtual wiring is set to half of the longest path, both the number of virtual pin pairs and the length of the virtual wiring are set. Since it is the maximum value that can be obtained, the channel area occupied by the wiring can be set to the maximum value that can be set, whereby all the wirings are always accommodated when a printed circuit board is actually manufactured. Therefore, there is no problem that wiring cannot be accommodated at the stage of producing a detailed wiring pattern, and a large amount of time is required for correction.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the wiring accommodation evaluation system of the present invention.

The wiring storability evaluation system according to the present embodiment uses a board size, a design standard, and the like before the external shape, layer configuration, connection structure between components, and standards of components to be arranged on the board are determined. (Line width, conductor spacing, via diameter, etc.),
The purpose of the present invention is to easily evaluate the wiring storability from a rough circuit configuration image using the number of layers as a parameter. The configuration includes a component placement unit 1, a component information definition unit 2, a board outline definition unit 3, a wiring accommodating calculation unit 4, a board information definition unit 5, and a virtual pin pair number calculation formula definition unit 6.

The component information definition unit 2 includes a component size, the number of pins, and a pin type (surface mounting /
In the portion that defines the contact hole, the board outer shape defining section 3 is a portion that defines the outer shape of the printed board. The component placement unit 1 arranges components defined by the component information definition unit 2 on the board outline defined by the board outline definition unit 3, and the board information definition unit 5 includes wiring width, wiring interval, via hole and through hole diameter. Is defined for each layer, and the virtual pin pair number calculation formula definition unit 6 is a portion for defining a calculation formula for calculating the number of virtual pin pairs, the virtual wiring length, and the number of via holes. The wiring accommodating calculation unit 4 includes the definition units 2, 3, 5,
Virtual pin pair number calculation formula definition part 6 from the information defined in
The wiring ratio is calculated by using the calculation formula defined in the above, and the wiring accommodating property is evaluated. Here, the input in the component placement unit 1 and each of the definition units 2, 3, 5, and 6 may be performed interactively using an input unit such as a mouse by a graphic display.

Next, a specific operation of the wiring accommodation evaluation system will be described.

First, a component information definition unit 2, a board outline definition unit 3, a board information definition unit 5, a virtual pin pair number calculation formula definition unit 6
Necessary information is defined in each definition section. Definition of these pieces of information may be performed in any order.

The component information definition unit 2 defines information on components to be mounted. Here, it is assumed that components A and B are mounted, and they are defined as follows. For part A,
As shown in FIG. 2A, the component size is set to “20 mm (vertical)
× 10 mm (horizontal) ”, the number of pins is“ 10 ”, the pin type is“ surface mount ”, and the pin size is“ 1 mm (vertical) × 5 mm
(Horizontal) ", and the mounting surface is defined as a" table ". As for the part B, as shown in FIG.
(Vertical) x 10 mm (horizontal) ", the number of pins is" 10 ", the pin type is" surface mount ", and the pin size is" 1 mm (vertical) x
5 mm (horizontal) "and the mounting surface as" back ".

The board outline defining section 3 defines the outline of the printed circuit board. Here, as shown in FIG. 3, the substrate size is defined as “500 mm (length) × 300 mm (width)” and the number of layers is defined as “two layers”.

The board information definition section 5 defines the wiring width, wiring interval, via hole diameter and through hole diameter of the wiring pattern on the substrate for each layer. Here, as shown in FIG. 4, the wiring width was defined as "1 mm", the wiring interval was defined as "3 mm", and the via hole diameter was defined as "2 mm". Note that parts A,
When the pin type of B is a through-hole mounting, the through-hole diameter is defined instead of the via-hole diameter.

The number-of-virtual-pin-pairs calculation formula definition unit 6 includes the number of virtual pin pairs, the virtual wiring length,
Each formula for calculating the number of via holes is defined. Here, as shown in FIG. 5, assuming that the number of pin pairs between components A and B, the average of the wiring length, and a predetermined ratio of the number of virtual pin pairs become the number of via holes, the number of virtual pin pairs = (Number of front surface pins + number of back surface pins) ÷ 2 (1) virtual wiring length = number of virtual pin pairs × (substrate vertical + substrate horizontal) ÷ 2 (2) number of via holes = number of virtual pin pairs × 0. 2 ... (3)

The definitions in the component information definition unit 2 and the board outline definition unit 3 are interactively performed, and the definitions in the board information definition unit 5 and the virtual pin pair number calculation formula definition unit 6 are defined in advance as files. I do.

When all the definitions are made as described above, the wiring accommodation calculation unit 4 sets the component information definition unit 2, the board outline definition unit 3,
Then, the total channel area and the occupied channel area of the wiring are calculated based on the information defined by the board information defining unit 5, and the ratio of the occupied channel area of the wiring to the total channel area is calculated as the wiring accommodating property. Hereinafter, the calculation of the wiring accommodation capacity will be specifically described.

In calculating the occupied channel area of the wiring, first, a virtual pin pair number calculation formula definition unit is defined based on the component information defined by the component information definition unit 2 and the board size defined by the board outline definition unit 3. Formula (1) defined in 6
Using (3), the number of virtual pin pairs, the virtual wiring length, and the number of via holes are obtained.

[0029] In the virtual pin pair number = (10 + 10) ÷ 2 = 10 present wire length = 10 × (300 + 500) ÷ 2 = 4 000mm via hole number = ten × 0.2 = 2 pieces Here, the number of via holes of the substrate Is the minimum number of via holes that connect the front and back, and the number of pin pairs that connect the front and back.

Since the channel area occupied by the component pins is obtained as (number of pins) × (channel occupied by the pins), 1 mm × 5 mm × 10 × 2 components = 100 mm ² . Wiring channel area (virtual wiring and component pin and via hole) is occupied, since required as wire length × wiring width + pin area + via hole area × layer number, 4 000 × 1 + 100 + 6 × 2 = 4112 mm 2 Becomes

The total channel area of the substrate can be calculated by calculating the channel area per layer by dividing the vertical and horizontal sizes of the substrate by the wiring intervals, and multiplying this by the number of layers. (300 ÷ 3) × (500 ÷ 3) × 2
Layer = 33200 mm ² .

[0032] Quantifying wiring capacity as a percentage of the occupied channel area to the total channel area can be calculated as occupied channel area ÷ total channel area × 100 (%) = 4112 ÷ 33200 × 100 = 12.4% . If the numerical value (%) of the wiring accommodating property thus obtained is within 100%, all the wirings are always accommodated when the printed circuit board is actually manufactured.

In the above description, the wiring accommodating capacity is obtained as a ratio of the occupied channel area to the total channel area. However, the number of occupied channels and the total number of channels calculated on a grid basis are obtained. Is obtained as a ratio of the number of occupied channels to the total number of channels, it is possible to calculate wiring accommodating with higher accuracy. In this case, there is provided a grid definition unit for defining how many grid sizes are to be set by design rules, and the wiring accommodating calculation unit 4 determines the number of occupied channels and the total number of channels based on the defined grid size. By obtaining this, the wiring accommodating property is evaluated. When the grid is 1 mm × 1 mm, the result is the same as the above calculation result.

When the pin types of the components A and B are of the through-hole mounting type, the channel area occupied by the wiring, the component pins, and the via holes is calculated as virtual wiring length × wiring width + through hole area × number of layers. Can be similarly calculated. The through-hole area in this case is ( half -hole diameter of through-hole) ² × 3.14 × the number of component pins.

Further, the above-described calculation expressions (1) to (3) (the number of virtual pin pairs, the length of the virtual wiring, and the number of via holes) are merely examples, and the present invention is not limited to these. If it is lower than 100%, it is only necessary that all wiring can be accommodated when a printed circuit board is actually manufactured.

[0036]

According to the present invention configured as described above, before determining the details of the circuit, the board size, design criteria (line width, conductor spacing, via diameter, etc.), the number of layers, and the like are used as parameters. Since it is possible to easily evaluate wiring accommodability from a rough circuit configuration image, wiring can not be accommodated at the stage of creating a detailed wiring pattern, and it is not necessary to spend a lot of time on correction, There is an effect that efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a wiring accommodation evaluation system of the present invention.

FIGS. 2A and 2B are diagrams illustrating an example of component information definition.

FIG. 3 is a diagram showing an example of a board outline definition.

FIG. 4 is a diagram illustrating an example of a board information definition.

FIG. 5 is a diagram illustrating an example of a calculation formula definition.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dialog component placement part 2 Component information definition part 3 Board outline definition part 4 Wiring accommodating calculation part 5 Board information definition part 6 Virtual pin pair number calculation formula definition part

Claims (8)

(57) [Claims] 1. A method for evaluating wiring storability when designing a wiring pattern by arranging components on a printed circuit board, wherein the number of pins and the pin type of the components arranged on the printed circuit board are defined. A first step, a second step of defining the size and the number of layers of the printed circuit board, a third step of defining a width and interval of the wiring pattern, a via hole diameter, and a through hole diameter, and the printed circuit board A fourth step in which the number of virtual pin pairs that can be paired between the components arranged in the virtual pin pair is の of the sum of the pins of both components, and the length of the virtual wiring connecting the pins of the virtual pin pair A fifth step of setting the length to one half of the longest path obtained from the vertical and horizontal sizes of the printed circuit board; and setting the vertical and horizontal sizes of the printed circuit board to the wiring, respectively. A sixth step of calculating a channel area per layer by dividing by a pattern interval, and calculating a total channel area of the printed circuit board by multiplying this by the number of layers; and when the pin type of the component is a surface mount type The number of pairs of a predetermined ratio of the number of virtual pin pairs as the number of via holes,
Calculate the channel area occupied by each pin of the virtual wiring and both components and the channel area occupied by the via hole in each layer, and determine the sum thereof as the occupied channel area.If the pin type of the component is through-hole mounting, Calculating the channel area occupied by the virtual wiring and the channel area occupied by the through-holes corresponding to the pins of the two components in each layer, and taking the sum as the occupied channel area, and calculating the occupied channel with respect to the total channel area. A seventh aspect of the present invention includes a seventh step of evaluating a wiring accommodating property by obtaining a ratio of an area. 2. The wiring accommodating evaluation method according to claim 1, wherein the total channel area and the occupied channel number calculated in the seventh step are divided into lattice units to reduce the total channel number and the occupied channel number. A wiring accommodating property evaluation method, wherein the wiring accommodating property is evaluated by calculating the ratio of the number of occupied channels to the total number of channels. 3. The wiring accommodation evaluation method according to claim 1, wherein the definitions performed in the first to third steps are interactively performed by a graphic display. 4. A system for evaluating wiring storability when designing a wiring pattern by arranging components on a printed circuit board, wherein the number of pins of the components arranged on the printed circuit board is defined as component information. Component information defining means, board shape defining means for defining the size and the number of layers of the printed board as board shape information, board information defining means for defining the width and interval of the wiring pattern, via hole diameter as board information, A calculation that defines a calculation formula for calculating the number of virtual pin pairs that can be paired, the average length of virtual wiring connecting the pins of the virtual pin pair, and the number of via holes between the components arranged on the printed circuit board. Formula definition means, and the number of virtual pin pairs between components arranged on the printed circuit board using the calculation formula from the component information, board outline information, and board information Wire length, calculates the number of via holes, to calculate the channel area occupied by the wirings on the basis of the calculated output result, and calculates the total channel area of the printed circuit board,
A wiring accommodation evaluation system comprising: a wiring accommodation raw calculation means for calculating the wiring accommodation from the ratio of the occupied channel area to the total channel area. 5. A wiring board in which components are arranged on a printed circuit board.
A system that evaluates wiring accommodability when designing turns
Then, the number of pins of the components arranged on the printed circuit board is determined by the component information.
Component information defining means for defining the size and number of layers of the printed circuit board as board information
Board outline defining means, and the width and interval of the wiring pattern and the diameter of the through hole.
A pair is defined between the board information defining means defined as board information and the components arranged on the printed circuit board.
DOO number of virtual Pinpe A which can, between pins of said virtual pin pairs
Average length of virtual wiring connecting through holes, occupied by through holes
Formula definition method to define the formula to calculate each area
Step and the component information, board outline information, board information from the above formula
Based on the result calculated using
Calculate the area of the printed circuit board
Calculate the channel area and calculate the occupied channel with respect to the total channel area.
Wiring accommodating livelihood that calculates wiring accommodability from the ratio of the tunnel area
And a calculating means . 6. The wiring accommodation evaluation according to claim 4 or 5.
In the pricing system, the components defined by the component information definition
A wiring storability evaluation system comprising a component arranging means for arranging on a defined board outer shape . 7. The wiring accommodation evaluation system according to claim 6.
System, component information definition means, board outline definition means, board information definition means
The step and component placement means are used for inputting information and component placement.
A wiring accommodation evaluation method characterized by being interactively performed . 8. The wiring accommodation evaluation system according to claim 6.
In the Further comprising a grid defining means for defining the size of the grid, The wiring accommodation raw calculation means calculates the total channel area and occupied channels.
The panel area is the case defined by the grid definition means.
To the total number of channels and the number of occupied channels.
From the ratio of the number of occupied channels to the total number of channels
Wiring accommodability evaluation characterized by calculating wiring accommodability
Method.