JP3165991B2 - Placement / wiring design method and wiring quality evaluation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention arranges and designs a plurality of electronic components to be mounted on a printed wiring board, and arranges and designs a wiring pattern for connecting the plurality of electronic components on the printed wiring board. Regarding the wiring design method, in particular, when a plurality of electronic components mounted on a printed wiring board are arranged by layout design, quality evaluation information necessary for evaluating the quality of wiring defined by the layout is output. The present invention relates to a wiring quality evaluation device.

[0002]

2. Description of the Related Art As is well known, an electronic device for realizing a predetermined function includes a plurality of electronic components. A plurality of electronic components are mounted (mounted) on a printed wiring board. The plurality of electronic components are connected to each other by a wiring pattern wired on a printed wiring board.

Therefore, in order to manufacture an electronic device, it is necessary to determine the arrangement of a plurality of electronic components on a printed wiring board and form a wiring pattern on the printed wiring board. For that purpose, first, it is necessary to arrange and design a plurality of electronic components mounted on the printed wiring board, and to design a wiring pattern on the printed wiring board. As is well known, such a design is a design using a computer (C
AD) technology. Here, since the layout design and the wiring design are related to each other, it is necessary to perform the layout and wiring design at once. That is, for example, even if the layout obtained by the layout design is optimal under predetermined circuit constraints, wiring may be difficult under such a layout. In such a case, relocation design is performed. This is repeated until it is determined that both the layout obtained by the layout design and the wiring obtained by the wiring design are good.

Conventionally, various arrangement design methods have been proposed. For example, Japanese Patent Laying-Open No. 4-340800 (hereinafter referred to as Prior Art 1) discloses an "optimal arrangement method of a surface mount component for mounting a printed wiring board". According to the prior art 1, when a two-way lead surface mount component is mounted on a printed wiring board and one or more printed wiring patterns pass between adjacent reflow pads, the longitudinal direction of the reflow pad is set to the component mounting surface side. Arrange them so as to be parallel to the printed wiring pattern. The two-way lead surface-mounted components to be mounted adjacent to each other are arranged such that the short sides of the reflow pads of the two-way lead surface-mounted components are parallel. As a result, the use of the holes with pads provided for connecting the pins of the component with the conductor can be reduced, and high-density wiring can be realized.

[0005] Another arrangement design method is disclosed in Japanese Patent Laid-Open No. 4-28607.
Japanese Patent Application Publication No. 7 (hereinafter referred to as Prior Art 2) discloses a “parts automatic layout design method for printed wiring boards”. The wiring design method disclosed in the prior art 2 includes circuit block forming means, connection information classifying means, circuit block connection information determining means, circuit block layout designing means, and circuit block component layout designing means. The circuit blocking means groups components into circuit blocks for each circuit function on the printed wiring board. The connection information classifying means divides all the components in each grouped circuit block into connection information to be closed in the circuit block and connection information to be connected between the circuit blocks. The circuit block connection information determination means determines the strength of connection information between circuit blocks. The circuit block layout design means determines the area occupied by each circuit block from the sum of the external dimensions of each component. The circuit block component layout design means designs the layout of each circuit block based on the connection method between the circuit blocks and the signal flow, and then designs the layout within the circuit block. As a result, it is possible to design the optimal arrangement of components along the signal flow.

Further, Japanese Patent Application Laid-Open No. 4-36872 (hereinafter referred to as Prior Art 3) discloses an "electronic component mounting process design support system". According to the prior art 3, the stored data relating to the specifications of the printed wiring board, the electronic components, and the provisional arrangement data is transferred to the analysis unit online. The electronic components are temporarily placed on the printed wiring board on the CRT, and the simulation is repeated until the desired reliability is obtained. The board is manufactured by transferring the optimal arrangement data obtained after the completion of the simulation to a designing unit and a manufacturing unit that design a pattern for a printed wiring board. As a result, the simulation process is inlined, and a highly reliable product can be obtained in a short time. In addition, there is no need for a prototype stage, and development costs can be reduced. Here, when a wiring pattern of the printed wiring board is created in the design unit, when it is extremely difficult to manufacture the printed wiring board or when the electrical characteristics cannot satisfy a desired value, the feedback is sent back to the analysis unit again. The model is corrected and simulated, and the process is repeated until the optimal layout is possible.

As described above, the above prior arts 1 and 2
Discloses only the layout design method. In the above-described prior art 3, the layout design is performed first, and then the wiring design is performed. When the wiring by the wiring design is difficult, the layout design is performed again. In other words, the layout design and the wiring design are performed independently.

[0008] Further, with the increase in the density of surface mount components, it has become difficult to automate placement. In this case, the layout design is performed manually.

Referring to FIG. 7, in the conventional placement / wiring design method, first, placement is designed (step S'1). This layout design may be performed manually or using CAD technology. After the layout design, an automatic wiring process is performed (step S'2). Based on the result of the automatic wiring execution, the quality of the wiring is evaluated (step S′3). Here evaluation is not good (NG)
If it is determined that it is, the process returns to step S′1 to change the arrangement. If the evaluation is determined to be good (OK) in step S′3, the wiring pattern is corrected (step S ′).
4).

[0010]

As described above, in the conventional placement / wiring design method, the quality of the wiring is evaluated based on the result of the automatic wiring execution. This method requires a long time for the automatic wiring process (step S'2), and thus has the following problem. The turnaround time (TAT) of the pattern design increases. The number of steps for returning to the pattern design increases.

An object of the present invention is to provide an arrangement / wiring design method capable of reducing the TAT of pattern design.

Another object of the present invention is to provide an arrangement / wiring design method which can reduce the number of steps required for pattern design.

Still another object of the present invention is to provide a wiring quality evaluation apparatus for outputting quality evaluation information necessary for evaluating the quality of wiring before designing wiring.

[0014]

According to a first aspect of the present invention , there is provided an arrangement / wiring design method in which a plurality of electronic components to be mounted on a printed wiring board are arranged and designed, and the printing is performed. An arrangement / wiring design method for designing a wiring pattern for connecting the plurality of electronic components on a wiring board, the method comprising:
Arranging and designing the plurality of electronic components on arbitrary coordinates , the printed wiring board
A cut line parallel to the X axis and the Y axis is set
The number of pin pairs crossing the cut line and the cut line
On the cut line due to the channel capacity on the
The predicted channel usage rate, and
Use prediction channel in X and / or Y axis
A step you output as a distribution diagram, the predicted channel used
Determining the acceptability of the wiring based on the distribution map; and, when the determination is negative in the determining step, returning to the layout design step to rearrange the plurality of electronic components; And determining the wiring pattern on the printed wiring board when it is determined to be good. Second aspect of the present invention
Layout and wiring design methods on printed wiring boards
Arrange and design multiple electronic components to be mounted, and
For connecting the plurality of electronic components on a printed circuit board.
This is an arrangement / wiring design method for designing wiring patterns.
And the positions on the printed wiring board are orthogonal to each other by X
Axis and Y-axis coordinates.
Arranging and designing the electronic component,
Specified part information and parts obtained in the above layout design step
Based on the product arrangement information and the connection information between parts,
The X component length and Y component length of all parts represented by the
The predicted total wiring length represented by the sum and the predicted total wiring length
Estimated by dividing by the total routable length of the printed wiring board
Calculating a gross channel utilization rate; and
Based on the total wiring length and the estimated total channel utilization,
The step of determining the quality of the wiring and the step of determining
The electronic components are redistributed when it is determined that
Step to return to the above layout design step to place
And when it is determined to be good in the above determination step,
Steps for designing wiring patterns on printed wiring boards
And the top. Placement / wiring arrangement according to the third aspect of the present invention
Metering method can be implemented on multiple printed circuit boards.
Arrange and design the electronic components and place them on the printed circuit board.
Wiring patterns for connecting multiple electronic components
A layout and wiring design method for measuring
The position on the substrate is represented by the X-axis and Y-axis coordinates orthogonal to each other.
And design the multiple electronic components on arbitrary coordinates
And X on the printed circuit board.
Axis, and a cut line parallel to the Y axis is provided.
The number of pin pairs that cross the in
Channel on the cut line
The estimated channel usage rate in the X-axis direction and
And / or Y-axis as predicted channel usage distribution map
And electronic component information defining the electronic component.
Component placement information and parts obtained in the above placement design step
Based on the connection information between parts, the
Predicted by the sum of the X and Y component lengths of all components
The total wiring length and the estimated total wiring length
Estimated total channel utilization obtained by dividing by the total routable length
Calculating the predicted channel use distribution map
And the estimated total wiring length and the estimated total channel usage rate.
And determining whether the wiring is good or bad.
When it is determined to be no in the step, the plurality of electronic units
Return to the above layout design step to relocate the product.
Tep and that it was determined to be good in the above determination step
Wiring design on the printed wiring board
Steps.

Further, according to the fourth aspect of the present invention , the X-axis and the Y-axis orthogonal to each other obtained by the layout design .
A wiring quality evaluation device that outputs quality evaluation information necessary for evaluating the quality of wiring defined by the arrangement of a plurality of electronic components mounted on a printed wiring board having a position represented by coordinates , A wiring quality evaluation device that outputs the quality evaluation information based on component information representing the electronic component and component placement information and inter-component connection information obtained from the layout design ;
A cut line parallel to the X axis and the Y axis is provided;
The number of pin pairs crossing the cut line and the cut line
On the cut line due to the above channel capacity
A predicted channel usage rate is obtained, and the predicted channel usage rate is X
Predicted channel usage distribution in the axial and / or Y-axis directions
Having a channel usage distribution prediction unit for outputting as a diagram,
The predicted channel usage distribution chart is output as pass / fail evaluation information.
Thus, an apparatus for evaluating the quality of wiring can be obtained.
According to a fifth aspect of the present invention, an arrangement
Represented by X-axis and Y-axis coordinates orthogonal to each other.
Multiple electrons mounted on a printed wiring board with positions
Evaluate the quality of wiring specified by component placement.
Quality evaluation device that outputs the quality evaluation information necessary for
Wherein component information representing the electronic component and the layout design
Based on component placement information and component connection information
A wiring quality evaluation device for outputting the quality evaluation information.
In all the parts indirectly indicated by the connection information between parts
Estimated total wiring length represented by the sum of the X component length and the Y component length
A total wiring length prediction unit for obtaining the estimated total wiring length,
Prediction obtained by dividing by the total routable length of the printed wiring board
A total channel utilization prediction unit for calculating the total channel utilization
Having the predicted total wiring length and the previous as the quality evaluation information.
And outputting the estimated total channel usage rate.
A wiring quality evaluation device is obtained. According to a sixth aspect of the present invention,
Then, the X-axis and the orthogonal
And printed wiring board having a position represented by Y-axis coordinates
Specified by the arrangement of multiple electronic components mounted on the board
Pass / fail evaluation information required to evaluate pass / fail of wiring
A wiring quality evaluation device that outputs
Component information to represent and component placement information obtained from the layout design
And on the basis of the inter-part connection information, before Symbol quality evaluation information
In the wiring quality evaluation device that outputs a report,
A cut line parallel to the X axis and the Y axis is placed on a wiring board.
The number of pin pairs crossing the cut line and the
The cut line depends on the channel capacity on the cut line.
Determining the predicted channel usage rate above,
Predict usage rate in X-axis and / or Y-axis direction
Channel usage distribution predictor that outputs as a usage distribution map
And the X component of the connection between all components indicated by the connection information between components.
Obtain the estimated total wiring length represented by the sum of the division length and the Y component length
A total wiring length prediction unit, and the printed wiring length
Estimated total channel obtained by dividing by the total routable length of the printed circuit board
And a total channel usage rate prediction unit for determining
The predicted channel use distribution diagram as the quality evaluation information
Output the predicted total wiring length and the predicted total channel usage rate
A wiring quality evaluation device is obtained.

Further, according to the seventh aspect of the present invention , the X-axis and the Y-axis orthogonal to each other obtained by the layout design.
A wiring quality evaluation device that outputs quality evaluation information necessary for evaluating the quality of wiring defined by the arrangement of a plurality of electronic components mounted on a printed wiring board having a position represented by coordinates Based on board information representing the printed wiring board and component placement information obtained from the layout design, component connection information and component pin information,
Wiring acceptability evaluation device smell to output the acceptability evaluation information
Providing a cut line on the printed wiring board,
Pattern that predicts the distribution of the pattern on the cut line
Distribution prediction unit and the number of pin pairs crossing the cut line
And the cut according to the allowable number of wires on the cut line
Predict channel utilization on the line and calculate the predicted channel
Predict usage rate in X-axis and / or Y-axis direction
Channel usage distribution predictor that outputs as a
Using the prediction channel as the quality evaluation information.
A wiring quality evaluation apparatus characterized by outputting a distribution map for use . According to the eighth aspect of the present invention, the layout design
In the X-axis and Y-axis coordinates obtained from
Mounted on a printed wiring board with the indicated position
The quality of wiring specified by the arrangement of multiple electronic components
Wiring quality that outputs quality evaluation information required for evaluation
A rejection evaluation device, wherein the substrate represents the printed wiring board
Information and component layout information obtained from the layout design, between components
Based on the connection information and the component pin information,
In a wiring quality evaluation device that outputs value information,
Analyze the coordinate value of the pin with respect to the point and connect the pin pairs
And a pin coordinate analysis unit that analyzes the
Calculate the X component length and Y component length of the pair, and calculate the X component length of all pin pairs.
Total wiring that predicts the sum of the division length and Y component length as the total wiring length
Length prediction part and the wiring prohibition part in the printed wiring board are excluded.
To analyze the total channel capacity indicating the routed area
A channel capacity analysis unit, the estimated total wiring length and the all channels
The overall capacitance of the printed wiring board
And a total channel utilization prediction unit that predicts the
The estimated total wiring length and the estimated total
Evaluation of wiring quality characterized by outputting channel usage rate
A charging device is obtained. According to a ninth aspect of the present invention, an arrangement
X-axis and Y-axis orthogonal to each other obtained by design
Mounted on a printed wiring board that has a position represented by coordinates
Wiring specified by the arrangement of multiple electronic components
Outputs information for quality evaluation required to evaluate quality
A wiring quality evaluation device, wherein the printed wiring board is displayed.
Board information and component layout information obtained from the layout design,
Based on the inter-part connection information and the part pin information,
In a wiring quality evaluation device that outputs quality evaluation information,
Analyze the coordinate value of the pin with respect to the origin of the board, and
A pin coordinate analysis processor that analyzes the flow
Calculate the X component length and Y component length of the
Is estimated as the total wiring length
A total wiring length prediction unit and a cut line on the printed wiring board.
And the distribution of the pattern on the cut line is predicted.
The pattern distribution prediction unit to measure
The number of pin pairs to cut and the allowable number of wires on the cut line
Predict the channel usage rate on the cut line,
The predicted channel usage rate in the X-axis direction and / or the Y-axis direction
Channel usage that is output as a predicted channel usage distribution chart
Distribution prediction unit, and a wiring prohibition unit in the printed wiring board
Analyzes the total channel capacity indicating the routable area except for
An all channel capacity analysis unit, the estimated total wiring length and the
Channel capacity, the overall printed circuit board
A total channel utilization prediction unit for predicting channel utilization
Using the predicted channel as the pass / fail evaluation information
Output distribution map, estimated total wiring length, and estimated total channel utilization
A wiring quality evaluation device is obtained.

[0017]

[Effect] Before the wiring design, the quality of the wiring is evaluated.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a layout and wiring design method according to an embodiment of the present invention. In the illustrated layout / wiring design method, layout design is first performed (step S1). This step S1 is called an arrangement design step. This layout design may be performed manually or using CAD technology. After the layout design, the quality of the wiring according to the present invention is evaluated as described later in detail (step S2). That is, in step S2, quality evaluation information necessary for evaluating the quality of the wiring specified by the arrangement obtained in step S1 is obtained. Subsequently, the quality of the wiring is determined based on the quality evaluation information (step S3). If the determination is negative (NG), the process returns to step S1 to change the layout. If the determination is good (OK) in step S3, automatic wiring processing is performed (step S3).
4) Then, the wiring pattern is corrected (Step S)
5).

As described above, the automatic wiring process (step S
Since the quality of the wiring is evaluated before performing the wiring design in 4), the TAT of the pattern design can be reduced, and the number of steps for returning the pattern design can be reduced.

With reference to FIG. 2, a description will be given of a wiring quality evaluation apparatus for performing wiring quality evaluation in step S2. The illustrated wiring quality evaluation device 10 includes a first file 20 for storing component information that specifies an electronic component,
A second file 30 storing the component arrangement information indicating the component arrangement obtained in step 2 and the inter-component connection information (pin pair information) indicating the connection relationship (pin pair) between the components, and an output device for outputting the output result 40.
The output device 40 is, for example, a printing device such as a printer or C
A display device such as an RT.

The wiring quality evaluation device 10 inputs component information from the first file 20 and component placement information and inter-component connection information from the second file 30, respectively. The wiring quality evaluation device 10 evaluates the quality of the wiring defined by the layout obtained in the layout design step based on the component information, the component layout information, and the inter-component connection information, as will be described in detail later. For quality evaluation necessary for the evaluation. The wiring quality evaluation device 10 outputs the obtained quality evaluation information to the output device 40 as an output result. In this example,
A predicted channel use distribution chart is output as pass / fail evaluation information.

Next, the wiring quality evaluation apparatus 10 will be described in more detail with reference to FIG. However, in this example,
The second file 30 stores board information in addition to the component arrangement information and the pin pair information. Here, the board information includes board size and wiring prohibited area data. The component arrangement information indicates a component origin coordinate value with respect to the substrate origin.

The illustrated wiring quality evaluation device 10 includes a first file input unit 11, a second file input unit 12, a channel usage distribution prediction unit 13, a total wiring length prediction unit 14,
And a total channel usage rate prediction unit 15.

The first file input unit 11 inputs component information from the first file 20. The second file input unit 12 inputs component arrangement information, pin pair information, and board information from the second file 30. The position of the printed wiring board is represented by X-axis and Y-axis coordinates orthogonal to each other. The channel use distribution prediction unit 13 performs
A predicted channel use distribution map representing predicted channel use rates in the X-axis direction and / or the Y-axis direction is obtained. The total wiring length prediction unit 14 calculates a predicted total wiring length of the connection between all components indicated by the pin pair information, as described later. This estimated total wiring length is represented by the sum of the X component length and the Y component length. As will be described later, the total channel usage rate prediction unit 15 obtains a predicted total channel usage rate obtained by dividing the predicted total wiring length by the total routable length of the printed wiring board. The wiring pass / fail evaluation device 10 outputs a predicted channel use distribution map, a predicted total wire length, and a predicted total channel use rate to the output device 40 as pass / fail evaluation information.

Next, a method of obtaining a predicted channel use distribution map in the channel use distribution predicting section 13 will be described.
The predicted channel use distribution diagram is a graph of the distribution of the channel use rate at each cut line as shown in FIG. 4, using a cut line method described later. FIG. 4 shows the distribution of the channel usage rate in the Y-axis direction.

Referring to FIG. 5, the cut line method will be described. Cut lines parallel to the X-axis and Y-axis are set at equal intervals on the printed wiring board, and the number of pin pairs crossing each cut line is counted. The distribution channel usage rate of the predicted channel usage distribution is calculated by the following Equation 1.

[0028]

(Equation 1) Here, α is the channel usage rate on the cut line, p is the number of pin pairs crossing the cut line, and c is the channel capacity (allowable number of wires) on the cut line. This channel usage rate is investigated for all cut lines in the X-axis and Y-axis directions, and a graph is shown as a predicted channel usage distribution diagram (see FIG. 4). In the example shown in FIG. 4, congestion of the channel usage rate is observed at the center, and it cannot be said that the wiring pattern is very good. As the wiring pattern, it is desirable that the channel use distribution is averaged.

Next, how to calculate the estimated total wiring length in the total wiring length prediction unit 14 will be described. What is the estimated total wiring length?
This is the total wiring length of all pin pairs, and is determined by the sum of the X component length and the Y component length.

When (X _ai , Y _ai ) and (X _bi , Y _bi ) are the start point and end point coordinates of the pin pair i, the estimated total wiring length is obtained by the following equation (2).

[0031]

(Equation 2) Here, L: estimated total wiring length, | X _ai −X _bi |: X component length of pin pair i, | Y _ai −Y _bi |: Y component length of pin pair i. Generally, the shorter the total wiring length, the better the wiring pattern.

Next, how to calculate the predicted total channel utilization rate in the total channel utilization prediction section 15 will be described. The estimated total channel use rate is obtained by the following equation 3 based on the total possible wiring length of the printed wiring board and the estimated total wiring length obtained by the above equation 2.

[0033]

(Equation 3) Here, β: predicted total channel usage rate, L: predicted total wiring length, L ₀ : total wiring available length in the board (channel capacity in the board)
It is. It can be said that a smaller predicted total channel use rate is a better wiring pattern.

In the following, the predicted total channel usage rate output from the wiring quality evaluation device 10 is compared with the actual total channel usage rate after the wiring pattern is designed, and the prediction accuracy of the wiring quality evaluation device 10 is evaluated. The results are shown in Table 1 below.

[0035]

[Table 1] Table 1 shows that although there are some errors, values that are almost close are obtained, and the effectiveness of the wiring quality evaluation device 10 can be confirmed. That is,
The wiring quality evaluation apparatus 10 can evaluate the quality of wiring before designing wiring. As a result, the arrangement can be changed so that the distribution of the wiring pattern (channel use distribution) can be averaged.
The number of undelivered lines in 4) can be reduced. Further, it is possible to reduce the number of steps for returning after the long-time automatic wiring process, and it is possible to reduce the number of wiring design steps by about 60% as compared with the related art.

Referring to FIG. 6, a description will be given of a wiring quality evaluation apparatus 10a according to a second embodiment of the present invention. The wiring quality evaluation device 10a includes a data input processing unit 12a, a pin coordinate analysis unit 16, a total wiring length prediction unit 14, a pattern distribution prediction unit 17, a channel use distribution prediction unit 13, a total channel capacity analysis unit 18 And the total channel utilization prediction unit 15
And Here, the channel usage distribution prediction unit 13, the total wiring length prediction unit 14, and the total channel usage rate prediction unit 15
Are the same as those shown in FIG. 3, and their description is omitted.

The data input processing unit 12a includes board information (board size, wiring prohibited area data), component placement information (component origin coordinate value with respect to the board origin), inter-component connection information (pin pair), component pin information (with respect to the component origin). Pin coordinates)
And register it in the table. Pin coordinate analysis unit 16
Analyzes the coordinate values of the pins with respect to the substrate origin, and analyzes the connection of the pin pairs. The pattern distribution prediction unit 17 provides a cut line on the printed wiring board, and predicts the pattern distribution on the cut line. The all-channel capacitance analyzing unit 18 analyzes a routable area (routable length) in the printed wiring board excluding a wiring prohibition unit.

The wiring quality evaluation device 10a includes the output device 4
In addition, as a wiring evaluation result (information for quality evaluation), a predicted channel use distribution map, a predicted total wiring length, and a predicted total channel
Output usage rate.

It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various changes / modifications can be made without departing from the gist of the present invention. For example, the pass / fail evaluation information may include a predicted channel use distribution map or a predicted total wiring length and the like .
And / or estimated total channel utilization or
You may make it output both .

[0040]

As described above, according to the present invention, the quality of the wiring can be evaluated before the wiring is designed, so that the arrangement can be changed so that the distribution of the wiring pattern (channel use distribution) can be averaged. Become. Further, the number of unassigned lines in the automatic wiring process can be reduced. Further, the number of steps for returning after the long-time automatic wiring processing can be reduced, and the number of wiring design steps can be reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a placement / wiring design method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a wiring quality evaluation device that performs the wiring quality evaluation shown in FIG. 1;

FIG. 3 is a block diagram showing a wiring quality evaluation apparatus according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a channel usage distribution predicted by a channel usage distribution prediction unit in FIG. 3;

FIG. 5 is a diagram for explaining a cutline method performed by a channel use distribution prediction unit in FIG. 3;

FIG. 6 is a block diagram showing a wiring quality evaluation apparatus according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing a conventional placement / wiring design method.

[Explanation of symbols]

 10, 10a Wiring quality evaluation device 11 First file input unit 12 Second file input unit 12a Data input processing unit 13 Channel usage distribution prediction unit 14 Total wiring length prediction unit 15 Total channel usage rate prediction unit 16 Pin coordinate analysis unit 17 Pattern distribution prediction unit 18 All channel capacity analysis unit 20, 30 File 40 Output device

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ identification code FI H05K 13/00 H05K 13/00 Z (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/50 H05K 13 / 00

Claims (9)

(57) [Claims] An arrangement / wiring design method for arranging and designing a plurality of electronic components to be mounted on a printed wiring board, and designing a wiring pattern for connecting the plurality of electronic components on the printed wiring board. Wherein the X-axis and the X-axis orthogonal to each other
And designing the plurality of electronic components on arbitrary coordinates in parallel with the X-axis and the Y-axis on the printed wiring board.
Piercing the cut line
The number of channels and the channel capacity on the cut line.
Obtain the predicted channel usage rate on the cut line,
Predicted channel utilization in X and / or Y direction
In a step you output as the predicted channel use distribution map, and determining the quality of the wiring, based on the predicted channel using distribution diagram, when it is determined that not in the determination step, the plurality of electronic components re A placement and wiring design method, comprising: a step of returning to the placement design step for placement, and a step of designing a wiring pattern on the printed wiring board when the determination is good in the determination step. 2. A semiconductor device to be mounted on a printed wiring board.
Place and design a number of electronic components and place them on the printed circuit board
A wiring pattern for connecting the plurality of electronic components is arranged.
An arrangement / wiring design method for designing a line, the method comprising:
And the coordinates of the Y-axis.
The step of arranging and designing the child parts, the part information defining the electronic parts, and the arrangement design step.
Based on the component placement information and
X component of all parts represented by the connection information between parts
Predicted total wiring length represented by the sum of the length and the Y component length,
Divide the total wiring length by the total wiring length of the printed wiring board
To calculate the estimated total channel utilization
And the estimated total wiring length and the estimated total channel utilization.
Determining the quality of the wiring have, when it is determined that not in the determination step, the double
In order to relocate a number of electronic components,
Returning to the step, and when it is determined to be good in the determination step, the step
Steps to design wiring pattern on lint wiring board
And placement and wiring design methods including 3. A semiconductor device to be mounted on a printed circuit board.
Place and design a number of electronic components and place them on the printed circuit board
A wiring pattern for connecting the plurality of electronic components is arranged.
An arrangement / wiring design method for designing a line, the method comprising:
And the coordinates of the Y-axis.
Arranging and designing child components; and arranging on the printed wiring board parallel to the X axis and the Y axis.
Piercing the cut line
The number of channels and the channel capacity on the cut line.
Obtain the predicted channel usage rate on the cut line,
Predicted channel utilization in X and / or Y direction
Outputting as a predicted channel use distribution map, component information specifying the electronic component, and the layout design step.
Based on the component placement information and
X component of all parts represented by the connection information between parts
Predicted total wiring length represented by the sum of the length and the Y component length,
Divide the total wiring length by the total wiring length of the printed wiring board
To calculate the estimated total channel utilization
, The predicted channel use distribution map, the predicted total wiring length, and the
Judge the quality of the wiring based on the estimated total channel utilization
A step of, when it is determined that not in the determination step, the double
In order to relocate a number of electronic components,
Returning to the step, and when it is determined to be good in the determination step, the step
Steps to design wiring pattern on lint wiring board
And placement and wiring design methods including 4. An orthogonal arrangement obtained by an arrangement design .
For quality evaluation necessary for evaluating the quality of wiring defined by the arrangement of a plurality of electronic components mounted on a printed wiring board having a position represented by the X-axis and Y-axis coordinates A wiring quality evaluation device for outputting information, the wiring quality evaluation device outputting the quality evaluation information based on component information representing the electronic components and component placement information and inter-component connection information obtained from the layout design. In the apparatus , on the printed wiring board, parallel to the X axis and the Y axis.
Piercing the cut line
The number of channels and the channel capacity on the cut line.
Obtain the predicted channel usage rate on the cut line,
Predicted channel utilization in X and / or Y direction
Use channel output as predicted channel use distribution map
A distribution prediction unit, wherein the prediction is performed as the quality evaluation information.
A good wiring characterized by outputting a channel usage distribution map
Negative evaluation device . 5. The method according to claim 1 , wherein the orthogonal directions are obtained by an arrangement design.
Having a position represented by X-axis and Y-axis coordinates
Depending on the arrangement of multiple electronic components mounted on the printed circuit board,
Quality evaluation required to evaluate the quality of wiring specified in
A wiring quality evaluation device for outputting value information, comprising:
Component information representing child components and components obtained from the layout design
Based on the placement information and the connection information between parts,
In the wiring quality evaluation device that outputs evaluation information, the X component length of all inter-component connections indicated by the inter-component connection information
To calculate the estimated total wiring length represented by the sum of
A wire length predicting unit, and the total wiring length of the printed wiring board can be calculated based on the predicted total wiring length.
Total to get the estimated total channel utilization obtained by dividing by length
A channel utilization rate predicting unit, wherein the predicted total wiring length and the predicted
Wiring quality characterized by outputting total channel utilization
Negative evaluation device. 6. An orthogonal arrangement obtained by the layout design.
Having a position represented by X-axis and Y-axis coordinates
Depending on the arrangement of multiple electronic components mounted on the printed circuit board,
Quality evaluation required to evaluate the quality of wiring specified in
A wiring quality evaluation device for outputting value information, comprising:
Component information representing child components and components obtained from the layout design
Based on the placement information and the connection information between parts,
In a wiring quality evaluation device that outputs evaluation information, a wiring quality evaluation device is provided on the printed wiring board, the X-axis being parallel to the Y-axis.
Piercing the cut line
The number of channels and the channel capacity on the cut line.
Obtain the predicted channel usage rate on the cut line,
X-axis direction and / or Y-axis direction prediction channel utilization
Use channel output as predicted channel use distribution map
Distribution prediction unit and X component length of all inter-component connections indicated by the inter-component connection information
To calculate the estimated total wiring length represented by the sum of
A wire length predicting unit, and the total wiring length of the printed wiring board can be calculated based on the predicted total wiring length.
Total to get the estimated total channel utilization obtained by dividing by length
A channel usage rate prediction unit, wherein the predicted channel usage distribution map is used as the pass / fail evaluation information.
And the predicted total wiring length and the predicted total channel utilization.
Wiring quality evaluation device characterized by applying force. 7. An orthogonal pattern obtained by the layout design .
For quality evaluation necessary for evaluating the quality of wiring defined by the arrangement of a plurality of electronic components mounted on a printed wiring board having a position represented by the X-axis and Y-axis coordinates A wiring quality evaluation device that outputs information, based on board information representing the printed wiring board and component placement information obtained from the layout design, component connection information and component pin information, the quality evaluation information. In the output wiring quality evaluation apparatus , a cut line is provided on the printed wiring board, and the cut line is provided.
Pattern distribution that predicts the pattern distribution on the line
A prediction unit, and the number of pin pairs crossing the cut line and the cut line.
Check the cut line according to the allowable wiring
The channel usage rate and the predicted channel usage rate in the X-axis direction.
And / or Y-axis predicted channel usage distribution map and
And a channel use distribution prediction unit that outputs the predicted channel use distribution map as the pass / fail evaluation information.
And a wiring quality evaluation device . 8. An image which is orthogonal to each other and obtained by the layout design.
Having a position represented by X-axis and Y-axis coordinates
Depending on the arrangement of multiple electronic components mounted on the printed circuit board,
Quality evaluation required to evaluate the quality of wiring specified in
A wiring quality evaluation device for outputting value information, comprising:
Obtained from the board information indicating the lint wiring board and the layout design
Component placement information, connection information between components, and component pin information
Wiring quality for outputting the quality evaluation information based on
The evaluation device analyzes the coordinate values of the pins with respect to the origin of the board , and
A pin coordinate analysis processing unit that analyzes the distance and calculates the X component length and Y component length of the pin pair from the pin coordinate values
The sum of the X component length and Y component length of all pin pairs is calculated as the total wiring length.
The total wiring length prediction unit that predicts as a wiring and the wiring excluding the wiring prohibition unit in the printed wiring board are possible.
All channel capacity solution to analyze all channel capacity showing region
Analysis section, the estimated total wiring length and the total channel capacity,
Estimate overall channel utilization of printed circuit boards
A total channel usage rate prediction unit, and the predicted total wiring length and the predicted total channel as the pass / fail evaluation information.
Wiring quality evaluation device characterized by outputting
Place. 9. A method according to claim 9 , wherein the orthogonal directions are obtained by an arrangement design.
Having a position represented by X-axis and Y-axis coordinates
Depending on the arrangement of multiple electronic components mounted on the printed circuit board,
Quality evaluation required to evaluate the quality of wiring specified in
A wiring quality evaluation device for outputting value information, comprising:
Obtained from the board information indicating the lint wiring board and the layout design
Component placement information, connection information between components, and component pin information
Wiring quality for outputting the quality evaluation information based on
The evaluation device analyzes the coordinate values of the pins with respect to the origin of the board , and
A pin coordinate analysis processing unit that analyzes the distance and calculates the X component length and Y component length of the pin pair from the pin coordinate values
The sum of the X component length and Y component length of all pin pairs is calculated as the total wiring length.
A total line length predicting unit for predicting the cut length , and a cut line provided on the printed wiring board;
Pattern distribution that predicts the pattern distribution on the line
A prediction unit, and the number of pin pairs crossing the cut line and the cut line.
Check the cut line according to the allowable wiring
The channel usage rate and the predicted channel usage rate in the X-axis direction.
And / or Y-axis predicted channel usage distribution map and
Channel usage distribution prediction unit to output and output, and wiring is possible except for the wiring prohibition unit in the printed wiring board
All channel capacity solution to analyze all channel capacity showing area
Analysis section, the estimated total wiring length and the total channel capacity,
Estimate overall channel utilization of printed circuit boards
A total channel use rate prediction unit, and the predicted channel use distribution map as the quality evaluation information.
And the estimated total wiring length and the estimated total channel utilization.
And a wiring quality evaluation device.