JP2001067390A - Design device for printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade a trouble in a designing step of a printed circuit board without relying on the experiences and perception of an expert. SOLUTION: This device includes a circuit diagram input tool 302 which produces a circuit according to the part information showing the parts to be mounted on a printed circuit board and the connection information on the interconnection of the parts, a layout input tool 303 which performs a layout about the arrangement of component parts of the circuit board and the circuit on the basis of the circuit diagram produced by the tool 302, an input part 304 which inputs the information to be given to both tools 302 and 303, a display part 305 which shows the circuit diagram information produced by the tool 302 and the layout information obtained by the tool 303 and an estimation means 307 which estimates an impedance discontinuous part on the basis of the layout information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for designing a printed circuit board used in an electronic device, and more particularly to an apparatus for designing a printed circuit board for estimating impedance discontinuities of wiring on a printed circuit board.

[0002]

2. Description of the Related Art In recent years, while the performance of electronic devices has been improved, the weight, thickness and size of electronic devices have been remarkably reduced as represented by mobile phones. Along with this, the configurations of printed circuit boards used in these electronic devices have become more complex, components and wiring have been mounted at a high density, and the distance between components and wiring has become extremely short.

[0003] The practical use of build-up boards in recent years has spurred such high-density mounting. For this reason, conventionally, the design of the printed circuit board, which was manually performed,
The design has been changed to a mechanized design using a printed circuit board design device (PCB-CAD), and various printed circuit board design devices have been commercialized. In recent years, a printed circuit board design device having an interface to a circuit simulator, a transmission line simulator, and the like has been put into practical use. In such a printed circuit board design device, a defect is detected and removed in advance by simulation at the board design stage. Attempts have been made.

FIG. 12 shows a configuration of a general printed circuit board designing apparatus conventionally used. The printed board design apparatus 101 is configured to be able to create a circuit diagram and lay out components and wiring. The printed circuit board design apparatus 101 includes a circuit diagram input tool 102, a layout input tool 103, and a design rule check tool 106, and an input unit 10 for inputting necessary information.
4. A display unit 105 for displaying a circuit diagram, components, and a wiring layout of a circuit in the course of design or for which design has been completed is additionally provided. The circuit diagram input tool 102 described above creates a circuit diagram based on components input from the input unit 104 and information on connections between the components. The layout input tool 103 is created by the circuit diagram input tool 102. Based on the obtained circuit diagram, a layout relating to the arrangement of components, wiring, and via holes is performed. The design rule check tool 106 is for determining whether the designed printed circuit board satisfies the design rules.

[0005] A flow chart of FIG. 13 shows a process of designing and manufacturing a printed circuit board using the above-described printed circuit board designing apparatus. This will be described below. First, in step 201, the board designer uses the circuit diagram input tool 102, the input unit 104, and the display unit 105 to set the component names, terminal names, components and components, and connections between terminals and terminals on the printed circuit board. Enter information. Next, in step 202, based on the circuit diagram created by the circuit diagram input tool 102, the layout input tool 103, the input unit 104, and the display unit 105
Component layout of C chip components, connectors, etc. is performed.
Thereafter, it is visually inspected or not using the design rule check tool 106 to determine whether or not a defect occurs in the created component arrangement (step 209), and it is determined whether or not a defect occurs (203).

Here, when it is determined that a problem occurs,
Alternatively, if it is determined by the design rule check tool 106 that a failure occurs, step 202
Return to and perform component rearrangement. On the other hand, if it is determined in the inspection of step 203 that no defect occurs, or if it is determined, the process proceeds to step 204, where the layout input tool 103, the input unit 104, and the display unit 10
5, the wiring layout of signal lines, ground wiring, via holes, and the like is performed. Thereafter, whether or not a defect occurs in the created wiring layout is visually inspected or inspected using the design rule check tool 106 (step 20).
9A), it is determined whether or not a problem occurs (205).

Here, when it is determined that a problem occurs,
Alternatively, if the design rule check tool 106 determines that a failure occurs, the cause is analyzed (205A), and if the cause is wiring, the process returns to step 204 to perform wiring layout. In addition, if the correction of the wiring layout alone does not solve the problem, and the component layout is determined to be inappropriate, the process returns to step 202 and the component is rearranged again.

In this way, it is determined that no problem occurs in the determination in step 205, or when it is determined, the process proceeds to step 206, where a prototype of the substrate is performed and an evaluation test is performed. In addition, Design Rule Check Tool 1
The timing of using 06 varies depending on various types of printed circuit board designing apparatuses.

In step 207, the performance of the prototype substrate is evaluated. If it is determined from the evaluation result that the desired specification is not satisfied, measures for the defective portion will be taken. In taking measures against this defective part, it is determined whether only the wiring layout needs to be corrected or the component arrangement needs to be corrected as well (2).
07A) Here, when it is determined that the component arrangement also needs to be corrected, the process returns to step 202 and the component arrangement is performed again. If it is determined that only the wiring layout needs to be corrected, the process returns to step 204 to rearrange the wiring layout. On the other hand, if it is determined to be acceptable in step 207, the process proceeds to manufacture (mass production) of a printed circuit board (step 208).

[0010] As described above, in the conventional printed circuit board design apparatus, the work of estimating a possible defect at the layout design stage and analyzing the evaluation result of the prototype board to extract the defective part is mainly performed by the board design. It was done based on the experience and intuition of the person, and often overlooked the defect.

The design rule check tool 10
In the case of No. 6 as well, it is possible to extract a defective portion where a manufacturing defect is likely to occur, but it is not possible to extract a defective portion where an electric defect is likely to occur, which may cause oversight of the defect. Had become. In addition, such problems related to unnecessary interference and unnecessary radiation have become extremely difficult to find due to the complexity of printed circuit boards and high-density mounting. In many cases, significant changes in component arrangement and wiring layout are accompanied.

As described above, if a defect is overlooked in the printed circuit board design stage, the defect is discovered after the trial production, and it is necessary to return to the board design stage and change the component arrangement and the wiring layout again. In general, such a series of operations is repeatedly performed many times before manufacturing and mass-producing a substrate having no defect, which requires much labor and a long development lead time.

This is not only for the development of printed circuit boards,
This has been a major factor in hindering product development efficiency and increasing the development period. As a countermeasure against such a problem, it is considered that a design rule check tool is sophisticated. However, the conventional design rule check tool issues a warning when a physical positional relationship on a printed circuit board, such as a wiring distance or a component distance, is too close to a predetermined manufacturable distance. However, the electric performance is not always taken into consideration. The design rule check tool does not issue a warning, and often causes electrical problems, for example, unnecessary interference and unnecessary radiation, which are two major defects on the printed circuit board, thereby improving the efficiency of printed circuit board development. Is hindering. To cope with such a problem, the invention according to Japanese Patent Application No. 9-50105 provides a means for estimating, extracting, and warning a possible failure point due to unnecessary interference between wirings at a board design stage. However, the above means is not always sufficient for estimating a possible failure point due to unnecessary radiation.

[0014]

As described above, conventionally, a defective part is extracted by evaluating a prototype substrate, and a measure against the defect is generally taken based on the experience and intuition of a skilled person. This requires labor and development lead time, which hinders not only the development of printed circuit boards but also the efficiency of product development.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a printed circuit board design capable of avoiding inconveniences at the board design stage regardless of the experience and intuition of a skilled person. It is to provide a device.

[0016]

In order to achieve the above object, according to the present invention, there is provided a circuit diagram for creating a circuit in accordance with component information indicating components mounted on a printed circuit board and connection information relating to connections between the components. Input means, layout input means for laying out the layout of the printed circuit board and circuit components based on the circuit diagram created by the circuit diagram input means, and the circuit diagram input means and the layout input means. An input unit for inputting power information, a display unit for displaying circuit diagram information created by the circuit diagram input unit, and layout information obtained by the layout input unit, respectively, based on the layout information. The printed circuit board designing apparatus is provided with an estimation means for estimating the impedance discontinuity. With such a configuration, the impedance discontinuity part, which is a main cause of unnecessary radiation, can be automatically estimated and extracted from the wiring layout during or after the design,
Since the component arrangement and the wiring layout can be corrected based on this extraction result, it is possible to detect and remove defects at the design stage before trial production of the printed circuit board. This makes it possible to improve the efficiency of printed circuit board development and the efficiency of product development.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A printed circuit board designing apparatus according to an embodiment of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 shows a configuration of a first embodiment of a printed circuit board designing apparatus according to the present invention. Printed circuit board design equipment 3
Reference numeral 01 includes a computer such as a CPU and a memory, and has a circuit diagram input tool 302, a layout input tool 303, a design rule check tool 306, and an impedance discontinuity estimating means 307 by a program. A part 305 is provided.

The circuit diagram input tool 302 creates a circuit diagram based on components input from the input unit 304 and information on connections between the components. The layout input tool 303 is a circuit diagram input tool. The layout relating to the arrangement of components, wiring, and via holes is performed based on the circuit diagram created in 302. The design rule check tool 306 is for determining whether the designed printed circuit board satisfies the design rules. Here, the difference between the design rule check tool 306 and the impedance discontinuity estimating means 307 is that the former design rule check tool 306 checks a layout defect with respect to a defect that occurs at the time of manufacture, whereas the latter design rule check tool 306 checks the latter. It is required that the discontinuous portion estimating means 307 checks a layout defect with respect to a defect that occurs when the electrical characteristics are evaluated.

An operation of designing a printed circuit board by the printed circuit board designing apparatus according to the first embodiment will be described with reference to a flowchart of FIG. First, at step 401, the board designer uses the circuit diagram input tool 302, the input unit 304, and the display unit 305 to connect a component name, a terminal name, a component to a component, and a terminal to a terminal arranged on a printed circuit board. Enter information. Next, in step 402, based on the circuit connection diagram created by the circuit diagram input tool 302, a layout input tool 303 and an input unit 304,
Using the display unit 305, layout of components such as ICs, chip components, and connectors is performed. Thereafter, it is visually inspected or checked by using the design rule check tool 306 whether or not a defect occurs in the created component arrangement (step 40).
9), it is determined whether or not a problem occurs (step 40)
3).

Here, when it is determined that a problem occurs, or when it is determined, the process returns to step 402 to relocate components. If it is determined in step 403 that no defect occurs, or if it is determined, in step 404, the layout input tool 303, the input unit 304, and the display unit 305 are used to output signal lines, ground lines, via holes, and the like. Wiring layout. Thereafter, it is visually inspected or checked using the design rule check tool 306 to determine whether or not a defect occurs in the created wiring layout (Step 410), and it is determined whether or not a defect occurs (Step 405). Here, when it is determined that a problem occurs or when it is determined, the cause is analyzed in step 405A, and if correction of the wiring layout can be dealt with, the flow returns to step 404 to perform wiring layout. If it is determined in Step 405A that the problem cannot be solved only by correcting the wiring layout, the process returns to Step 402 and the components are rearranged again.

Conventionally, in the process corresponding to step 410, it is visually inspected or checked using the design rule check tool 106 to determine whether or not a defect occurs in the created component arrangement. It is determined whether or not this is the case, and the evaluation has proceeded to the evaluation using the board prototype in step 406. However, in the printed circuit board design apparatus of the present invention, prior to the determination in step 405, step 41
At 0, the impedance discontinuous portion is estimated.

With this configuration, when the impedance discontinuity portion is extracted as a possible failure point, the user is prompted to perform the component layout 402 or the wiring layout 404 again as in the case of step 409 of the design rule check. Here, the judgment reference data regarding whether or not the estimated and extracted impedance discontinuity portion is a failure-possible portion is prepared in advance by a designer and impedance discontinuity is defined in the impedance discontinuity portion estimation means 307. It is incorporated as a database. For example, the impedance of the signal pattern is determined by parameters such as the distance L from the ground pattern, the dielectric constant εr of the material forming the printed circuit board, the width t and the length w of the signal pattern. A table is prepared by slightly changing the parameters, and a database is provided in which a flag indicates whether or not each state is impedance discontinuity when the state is not more than a predetermined value or not more than a predetermined value.

Further, as this database, a database which merely uses the change of characteristic impedance in a pattern as an evaluation function can be adopted, and a reflection coefficient of a discontinuous portion of the pattern, a VSWR (voltage standing wave ratio), and the like can be used. It is also possible to employ a transmission function that is an evaluation function. In short, since the impedance of each part of the pattern can be obtained from the layout information, it is sufficient to prepare a database having a criterion as to whether or not the impedance should be discontinuous when the impedance changes.

If the impedance discontinuous portion is not extracted in the impedance discontinuous portion estimation in step 410, this means that unnecessary radiation due to the impedance discontinuous portion has disappeared, which occurs when the electrical characteristics are evaluated. This means that the check for unwanted radiation has been completed. Therefore, the process proceeds from step 405 to step 406, where a prototype of the substrate is performed and the evaluation is performed.
Note that the timing (time) at which the impedance discontinuous portion is estimated may be after the wiring layout is completed or in the middle of the wiring layout, and may be performed at a timing that the designer wants to check.

Thereafter, in step 407, the performance of the prototype substrate is evaluated. If it is determined from the evaluation result that the desired specification is not satisfied, measures for the defective portion will be taken. In taking measures against this defective part, it is determined whether only the wiring layout needs to be modified or the component arrangement needs to be modified (407A). Here, the component arrangement also needs to be modified. If it is determined that there is, the process returns to step 402 and the components are arranged again. If it is determined that only the wiring layout needs to be corrected, the process returns to step 404 to rearrange the wiring layout. On the other hand, step 407
If it is determined to pass, the process proceeds to manufacturing (mass production) of a printed circuit board (step 408).

Next, a first modification of the present invention will be described. This first modified example is based on impedance discontinuity estimating means 3
07 is described. FIG. 3A schematically shows a cross section of the multilayer wiring board. First
It is assumed that the layer (L1) has a signal line (S), the second layer (L2), and the third layer (L3) have ground wirings (G) having different shapes. In this case, the characteristic impedance for the signal line of the first layer (L1) is arranged in the second layer (L2) and the third layer (L3) when there is no ground wiring near the signal line of the first layer (L1). Is defined as the impedance to the given ground wiring. However, in the case of the printed circuit board having the configuration shown in FIG. 3, the impedance with respect to the signal line (S) of the first layer (L1) becomes discontinuous at the point A.
Radiation resistance occurs at the point and unnecessary radiation occurs. Therefore, the point A is extracted from the data of the wiring layout as an impedance discontinuity portion, and is determined as a potential failure portion.

FIG. 5 shows the procedure. First, a signal line is found by referring to the wiring layout data (step 6).
01), calculate the distance from each grid point constituting the signal line to the closest ground wiring grid point (step 602). The distance between the lattice points can be calculated three-dimensionally using the information on the thickness direction of the substrate input in advance.

Next, when the distance from the ground wiring is not continuous at adjacent grid points on the signal line, that is, if the differential coefficient is not continuous, a wiring portion between the grid points is set in advance, for example. The determined failure database is referred to (step 603), the part is determined as an impedance discontinuity part (step 604), and a warning display such as blinking or changing color is displayed on the display unit 305 so that the part can be identified (step 605). . Here, the case of determining discontinuity can be changed by design, not only based on the failure database, but also, for example,
A comparison may be performed by setting a threshold value. Further, the signal line and the ground line can be distinguished from each other by attribute information added in advance by a signal line name or the like. By performing this series of operations on all signal lines on the board, it is possible to extract impedance discontinuities due to discontinuities in the positional relationship between the signal lines and the ground wiring, that is, possible failure points due to unnecessary radiation. Become. Here, the case where the signal line and the ground line are in different layers has been described.
As shown in (b), it is of course possible to similarly extract the case where the signal line (S) and the ground wiring (G) are in the same layer.

Next, a second modification of the present invention will be described. This second modification is different from the impedance discontinuity estimating means 3 in FIG.
07 illustrates another embodiment. FIG. 4 schematically shows a positional relationship between two signal lines in a certain layer on a printed circuit board. A first signal line (S1),
The second signal lines (S2) suddenly approach each other at point B. At this time, the impedance of the first signal line (S1) and the impedance of the second signal line (S2) become discontinuous at the point B due to the influence of the mutual signal lines. Radiation will occur. In this example, the point B is extracted as an impedance discontinuity portion from the data on which the wiring has been laid out, and is determined as a possible failure portion.

FIG. 6 shows the procedure. First, a signal line is found from the wiring layout data (step 80).
1) The distance from each grid point of the signal line to the closest grid point of another signal line is calculated (step 802). The distance between the grid points can be calculated using the coordinate values of the grid points.

Next, when adjacent grid points on a signal line are not continuous with other signal lines, that is, when the differential coefficients are not continuous, a wiring portion between the grid points is, for example, With reference to a preset failure database (step 803), it is determined as an impedance discontinuity part (step 804) and displayed on the display unit 305 (step 805).

In the above, when to determine the discontinuity can be varied depending on the design. In addition to using the fault database set in advance as described above, for example, a threshold may be set and compared. It is also possible to make the determination by performing the following. Further, the signal line and the ground line can be distinguished from each other by attribute information added in advance by a signal line name or the like. By performing this series of operations for all signal lines on the board, it is possible to extract impedance discontinuities due to discontinuities in the positional relationship between the signal lines, that is, potential failure points due to unnecessary radiation. . Here, the case where the signal line and the signal line are in the same layer has been described, but the case where the first signal line and the second signal line are in different layers can be similarly extracted.

Next, a third modification of the present invention will be described. This third modified example is a method for estimating the impedance discontinuity portion 3.
07 describes yet another embodiment. FIG.
Represents a positional relationship between a certain signal line (S) on the printed board and the outer shape of the printed board. The signal lines (S) are rapidly approaching each other at point C on the edge of the printed circuit board. At this time, the impedance of the signal line (S) is C
At that point, the change in the physical shape of the surroundings at the edge of the substrate becomes discontinuous, causing radiation resistance and unnecessary radiation. From the data on which the wiring is laid out, a portion having a positional relationship such as the point C is extracted as an impedance discontinuity portion, and is determined as a possible failure portion.

FIG. 9 shows the procedure. First, a signal line is found from the wiring layout data (step 90).
1) The distance from each grid point constituting the signal line to the nearest substrate edge is calculated (step 902).
The distance between the lattice point and the substrate edge can be calculated using the coordinate value of the lattice point and the coordinate value of the outer shape of the substrate.

Next, in a case where the distance between the adjacent grid points on the signal line and the edge of the substrate is not continuous, that is, the differential coefficient is not continuous, a wiring portion between the grid points is set in advance, for example. By referring to the set fault database (step 903), it is determined as an impedance discontinuity part (step 904) and displayed on the display unit 305 (step 905). Here, in what case the discontinuity is determined can be changed depending on the design, and not only based on the defect database but also, for example, a threshold value may be provided for comparison. By performing this series of operations for all signal lines on the board, it is possible to extract impedance discontinuities due to the discontinuity in the positional relationship between the signal lines and the board outline, that is, possible failure points due to unnecessary radiation. Becomes

Next, a fourth modification of the present invention will be described. This fourth modified example is an impedance discontinuous portion estimating means 3
07 illustrates another embodiment. FIG.
This is a schematic representation of a certain signal line on a print substrate. The line width of the signal line changes from W1 to W2 at point D. At this time, at point C, the impedance becomes discontinuous, radiation resistance occurs, and unnecessary radiation occurs. A portion where the line width changes, such as the point D, is extracted from the data on which the wiring is laid out, and is set as a possible failure portion.

FIG. 10 shows the procedure. First, signal lines are found from the wiring layout data (step 11).
1), calculate the wiring width of the signal line (step 11)
2). The portion where the wiring width is discontinuous is referred to, for example, a preset failure database (step 11).
3) It is determined as an impedance discontinuity part (step 114) and displayed on the display unit 305 (step 11).
5).

Here, the case in which discontinuity is determined can be varied depending on the design. In addition to using the fault database set in advance as described above, for example, a threshold value may be set and compared. It is also possible to make the determination by performing the following. By performing the above-described series of operations for all the signal lines on the substrate, it is possible to extract a discontinuous portion of impedance due to a change in signal line width, that is, a location where a failure may occur due to unnecessary radiation.

In the above embodiment, some means for automatically estimating and extracting the impedance discontinuity portion have been described. However, the impedance discontinuity portion can be estimated and extracted by other means. In some cases,
It is possible to realize the printed circuit board designing apparatus of the present invention.

FIG. 11 shows a configuration according to the second embodiment of the present invention. In addition to the above-described examples, there are impedance discontinuities on the substrate caused by a mismatch between the characteristic impedance of the wiring layout and the input / output impedance of the components mounted thereon. With respect to unnecessary radiation from this portion, the impedance discontinuity portion is extracted by using the impedance library 137 shown in FIG.

Here, the impedance library 137
Is a database in which the impedance characteristics of the individual components obtained in advance by measurement using the immediate base 138 or by simulation by the simulation unit 139 are stored as a library. Then, the characteristic impedance is calculated from the wiring layout data, and the calculated value and the impedance library 1 are calculated.
The impedance discontinuity estimating means 307 determines whether or not the impedance is discontinuous by comparing the input / output impedance stored in the memory 37 with the input / output impedance. As a result, it is possible to detect impedance discontinuity due to mismatch between the characteristic impedance of the wiring layout and the input / output impedance of the components mounted thereon, and to perform a design for removing the impedance discontinuity.

As described above, according to the embodiment of the present invention, the impedance discontinuity, which is a main cause of unnecessary radiation, is automatically estimated and extracted from the wiring layout during or after design. The component arrangement and the wiring layout can be corrected based on the extraction result. For this reason, in the evaluation after the trial production of the printed circuit board, it has become possible to take measures against the troubles based on the experience and intuition of a skilled person at the design stage without trial production of the printed circuit board. In addition, since a defective portion is automatically estimated and extracted from the wiring layout information, occurrence of a defect due to oversight can be avoided.

Thus, when developing a printed circuit board,
It is possible to reduce the cost of prototype board production, reduce the labor of skilled personnel, shorten the development period, etc., and further improve the efficiency, such as reducing the cost throughout the product development and shortening the development period. It becomes possible to plan. In recent years, the product development cycle of electronic devices represented by mobile phones is very short, and shortening the development period of such electronic devices and reducing development costs are very effective.

[0044]

As described above, according to the embodiment of the present invention, since the printed circuit board designing apparatus is configured by including the estimating means for estimating the impedance discontinuity based on the layout information, unnecessary radiation is achieved. The impedance discontinuity, which is the main factor, can be automatically estimated and extracted from the wiring layout during or after the design,
Since the component arrangement and the wiring layout can be corrected based on this extraction result, it is possible to detect and remove defects at the design stage before trial production of the printed circuit board. This makes it possible to improve the efficiency of printed circuit board development and the efficiency of product development.

[Brief description of the drawings]

FIG. 1 is a view showing a printed circuit board designing apparatus having an impedance discontinuous portion estimating means of the present invention.

FIG. 2 is a flowchart showing a flow of printed circuit board development using the printed circuit board design apparatus of the present invention.

FIG. 3 is a diagram for explaining a first modified example of the present invention.

FIG. 4 is a diagram for explaining a second modified example of the present invention.

FIG. 5 is a flowchart for explaining a first modified example of the present invention.

FIG. 6 is a flowchart for explaining a second modified example of the present invention.

FIG. 7 is a view for explaining a third modification of the present invention.

FIG. 8 is a view for explaining a fourth modification of the present invention.

FIG. 9 is a flowchart illustrating a third modified example of the present invention.

FIG. 10 is a flowchart illustrating a fourth modified example of the present invention.

FIG. 11 is a view showing a printed circuit board designing apparatus according to a second embodiment of the present invention using an impedance library.

FIG. 12 is a diagram showing a basic configuration of a conventional printed circuit board design device.

FIG. 13 is a flowchart showing a flow of conventional printed circuit board development.

[Explanation of symbols]

301 Printed circuit board design device 302 Circuit diagram input tool 303 Layout input tool 304 Input unit 305 Display unit 306 Design rule check tool 307 Impedance discontinuity estimation unit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hisao Iwasaki 3-1-1 Asahigaoka, Hino-shi, Tokyo F-term in the Toshiba Hino Plant (reference) 2G028 AA02 BF08 CG08 LR02 5B046 AA08 BA04 DA02 DA05 GA01 JA02 JA03

Claims (6)

[Claims] 1. A circuit diagram input means for creating a circuit in accordance with component information indicating components mounted on a printed circuit board and connection information on connections between the components, and a circuit diagram created by the circuit diagram input means. A layout input unit for performing a layout relating to the arrangement of the printed circuit board and circuit components based on the circuit diagram input unit; an input unit for inputting information to be provided to the layout input unit; and the circuit diagram input unit. And a display unit for displaying the circuit diagram information created by the above and layout information obtained by the layout input unit, respectively, and an estimating unit for estimating an impedance discontinuity based on the layout information. Printed circuit board design equipment. 2. The estimating means compares a positional relationship between a signal line and a ground,
2. The printed circuit board design apparatus according to claim 1, wherein the impedance discontinuity is estimated. 3. The apparatus according to claim 1, wherein said estimating means estimates an impedance discontinuity portion by comparing positional relationships between signal lines.
The printed circuit board design apparatus according to the above. 4. The estimating means compares the positional relationship between the signal line and the end of the substrate,
2. The printed circuit board design apparatus according to claim 1, wherein the impedance discontinuity is estimated. 5. The estimating means detects a portion where the line width of the signal line has changed,
2. The printed circuit board designing apparatus according to claim 1, wherein the impedance discontinuity section is provided. 6. The apparatus according to claim 1, wherein said estimating means estimates an impedance discontinuity based on a match / mismatch between input / output impedance of a component mounted on a printed circuit board and characteristic impedance of a wiring. PCB design equipment.