JP4283647B2 - Layout check system - Google Patents

Description

  The present invention relates to a CAD (Computer Aided Design) technique used for layout design of a printed wiring board (hereinafter referred to as a PCB), and more particularly to a PCB defined by layout data created using a CAD system. The present invention relates to a technique for checking whether a layout is a layout that effectively functions a bypass capacitor arranged on the PCB.

2. Description of the Related Art In recent years, high-performance digital ICs (hereinafter, referred to as high-speed ICs) that perform switching operations at high speed are used as main components of electronic devices as electronic devices become more sophisticated and digital.
A high-speed IC causes a high-frequency fluctuation in the power supply voltage and emits unnecessary radiation noise by performing a switching operation at high speed. For this reason, a PCB on which a high-speed IC is mounted is generally provided with a bypass capacitor in the vicinity of the power supply pin of the high-speed IC.

By arranging the bypass capacitor at an appropriate position, the high-frequency fluctuation of the power supply voltage generated by the high-speed switching operation of the high-speed IC is compensated by the charge stored in the bypass capacitor, and the high-frequency component is stabilized by the high-speed IC. An effect is obtained that unnecessary radiation noise can be confined around the high-speed IC by feeding back to the GND pin.
The layout of various components mounted on the PCB, the layout of wiring patterns, and the like are generally defined by layout data created by a layout designer using a CAD system. In creating the layout data, layout mistakes may occur where the bypass capacitor does not function effectively.

As a technique for checking whether or not there is such a layout error, there is a “printed circuit board wiring structure check system (hereinafter simply referred to as a check system)” disclosed in the following patent document.
In this check system, if the wiring structure of the wiring temporarily designed on the printed circuit board meets one of several error conditions prepared in advance, that is, the condition that the bypass capacitor does not function effectively, As an error, a countermeasure instruction for the error (hereinafter referred to as an error countermeasure instruction) is displayed.

For example, if one bypass capacitor is arranged corresponding to a predetermined number or more of high-speed IC power supply pins, or if a via exists between the bypass capacitor and high-speed IC power supply pin wiring path, an error countermeasure instruction Is displayed.
JP 2002-16337 A

However, there are some error conditions that cannot be checked by the above check system.
For example, if there is a power supply via on the wiring to which the power supply pin is connected, other than between the wiring path of the power supply pin of the high speed IC and the bypass capacitor, the bypass capacitor may not function effectively.

  In order for the bypass capacitor to function effectively, the impedance between the power supply pin and the bypass capacitor wiring path must be smaller than the impedance between the power supply pin and the power supply wiring path so that a high-frequency current flows toward the bypass capacitor. However, if the wiring distance between the power supply via and the power supply pin is shorter than the wiring distance between the power supply pin and the bypass capacitor, the impedance between the power supply pin and the power supply becomes smaller than the impedance between the power supply pin and the bypass capacitor. The bypass capacitor may not function effectively.

Since the above-described check system only checks whether a via exists in the wiring path between the bypass capacitor and the power supply pin of the high-speed IC, such an error condition cannot be checked.
In the above check system, an error countermeasure instruction is displayed when a via exists between the paths of the power supply pattern to which the bypass capacitor and the power supply pin of the high-speed IC are connected. However, this is not necessarily an error. There is a case.

  If it is assumed that the connection destination of the via is always the power plane, it may be judged as an error, but if the connection destination of the via is not the power plane but the power supply pattern of the line wiring, the power source of the connection destination It is necessary to consider the impedance between the wirings to the power supply of the pattern. In this case, since the impedance between the power supply pin and the power supply may be larger than the impedance between the power supply pin and the bypass capacitor, it is erroneous to determine that it is necessarily an error.

  The present invention relates to a layout check system capable of checking whether a layout of a PCB is a layout that effectively functions a bypass capacitor arranged on the PCB, and the system more accurately than a conventional check system. The purpose is to provide various technologies.

  In order to achieve the above object, a layout check system according to the present invention is a layout check system for checking layout data defining a layout of a power supply, a component having a power supply pin on a printed wiring board, and a bypass capacitor, The information including a basis for calculating a first value corresponding to an impedance between the power supply pin and the power supply and a second value corresponding to an impedance between the power supply pin and the bypass capacitor; Storage means for storing layout data; calculation means for calculating the first value and the second value based on the stored layout data; the calculated first value and the second value; And the layout allows the bypass capacitor to function effectively. Determination means for determining whether a bets, if a negative determination is made by the determination unit, and an outputting means for outputting the error information.

  The layout check method according to the present invention is a layout check method for checking layout data defining a layout of a power supply on a printed wiring board, a component having a power supply pin, and a bypass capacitor, the power supply pin and the Layout data including information serving as a basis for calculating a first value corresponding to an impedance between power supplies and a second value corresponding to an impedance between the power supply pin and the bypass capacitor is acquired. An obtaining step; a calculating step for calculating the first value and the second value based on the layout data; and comparing the magnitudes of the calculated first value and the second value. Determining whether the layout is a layout that effectively functions the bypass capacitor. If the determination step, the negative determination in said determination step is performed, characterized in that it comprises an output step of outputting the error information.

  A program according to the present invention is a program for causing a computer to perform a layout check process for checking layout data defining a layout of a power supply on a printed circuit board, a component having a power supply pin, and a bypass capacitor. The layout check process includes a basis for calculating a first value that is a value corresponding to an impedance between the power supply pin and the power supply, and a second value that is a value corresponding to an impedance between the power supply pin and the bypass capacitor. An acquisition step of acquiring layout data including information, a calculation step of calculating the first value and the second value based on the layout data, the calculated first value, and the second value Compare the magnitude of the values, the layout enables the bypass capacitor If a judgment step of judging whether a layout to ability, negative determination in said determination step is performed, characterized in that it comprises an output step of outputting the error information.

  Here, the value corresponding to the impedance refers to, for example, a wiring distance proportional to the magnitude of the impedance of the wiring, in addition to the value of the impedance itself.

  The layout check system, the layout check method, and the program having the above-described configuration have a first value that is a value corresponding to the impedance between the power supply pin and the power supply, and a second value that is a value corresponding to the impedance between the power supply pin and the bypass capacitor. By calculating and comparing, it is determined whether or not the checked layout is a layout that allows the bypass capacitor to function effectively. Therefore, it is possible to perform more accurate error determination than the check system described in the above publication.

  In addition, the calculating means calculates a first value that is the shortest wiring distance between the power supply pin and the power supply and a second value that is the shortest wiring distance between the power supply pin and the bypass capacitor based on the layout data. If the first value is smaller than the second value, the determining unit may determine that the layout is not a layout that effectively functions the bypass capacitor.

With this configuration, when the impedance between two points on the wiring is proportional to the distance, the shortest wiring distance between the power supply pin and the power supply, the power supply pin, and the bypass capacitor can be calculated without calculating the impedance value. By calculating the shortest wiring distance between them and comparing these sizes, it can be determined whether the checked layout is an error.
In the case where a power supply via is provided on the wiring connecting the power supply pin and the bypass capacitor, the calculation means can calculate the shortest wiring distance between the power supply pin and the power supply via based on the layout data. A first value and a second value that is the shortest wiring distance between the power supply pin and the bypass capacitor may be calculated.

  With this configuration, when the connection destination of the power supply via is the power supply plane and the impedance of the power supply plane is assumed to be 0, the shortest wiring distance between the power supply pin and the power supply via and the power supply can be calculated without calculating the impedance value. By calculating the shortest wiring distance between the pin and the bypass capacitor and comparing these sizes, it can be determined whether the checked layout is an error.

The storage means stores a threshold value, and the determination means compares the stored threshold value with the value of the ratio of the second value to the first value, and It may be determined whether the layout is a layout that effectively functions the bypass capacitor.
Further, the layout data includes wiring type information for identifying whether the wiring is a line or a surface, and for the wiring on the surface, size information indicating an area size is included, and the storage unit stores a prescribed value. The layout check system further includes, based on the wiring type information, analyzing means for analyzing whether or not the wiring connecting the power pin and the capacitor is a surface wiring, and as a result of the analysis, When it is found that the wiring connecting the power supply pin and the capacitor is a surface wiring, referring to the size information, it is determined whether or not the area size of the wiring on the surface is equal to or less than a stored specified value. A power plane determination unit that determines that the wiring on the surface is a specific power plane when the power supply plane is equal to or less than a specified value; When the wiring on the surface connecting between the capacitor and the capacitor is determined to be the specific power plane, the analyzing means further includes the specific power plane and the power source via the bypass capacitor based on the previous layout data. If the specific power plane and the power supply are found to be connected without passing through the bypass capacitor, the layout causes the bypass capacitor to function effectively. It may be determined that the layout is not achieved.

  With this configuration, it is possible to check whether or not the layout is such that unnecessary radiation noise generated from the power supply pins connected to the specific power supply plane does not leak from the specific power supply plane.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment described below is an example embodying the present invention, and does not limit the technical scope of the present invention.
<Embodiment 1>
<Overview>
The layout check system according to the first embodiment is a CAD system used for PCB layout design, and a layout designer creates layout data using this system.

  A feature of the layout check system according to the present embodiment is to check whether the layout of the PCB defined by the created layout data is a layout that effectively functions the bypass capacitor arranged on the PCB. Further, a value Z1 corresponding to the impedance between the power supply pin and the power supply of the high speed IC arranged on the PCB and a value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor are calculated, and the two calculated values are compared. If Z1 is smaller than Z2, an error is determined and error information is output.

<Configuration>
FIG. 1 is a diagram illustrating a functional configuration of the layout check system according to the first embodiment.
The layout check system 1 includes functional units such as a data input unit 9, a command input unit 10, a layout data creation unit 11, a layout check unit 12, a storage unit 13, and a display unit 14. Note that description of functions that are not necessary for describing the features of the present invention is omitted.

The layout check system 1 is a computer that includes hardware such as a CPU, an input device, an output device, and a storage device, and implements each function by the CPU executing a program stored in the storage device.
The data input unit 9 accepts input of circuit diagram data created using a circuit diagram design CAD device or the like. The received circuit diagram data is stored in the storage unit 13.

  The command input unit 10 receives a command input by a user operating an input device such as a keyboard and a mouse. The commands include, for example, a start command for starting a CAD application program, a drawing command for determining component placement and wiring patterns on a PCB layout diagram, and a layout check command for checking a created layout.

  The layout data creation unit 11 functions when the command input unit 10 receives an input of a start command from the user and the CAD application program starts, and the input circuit diagram data and the command input unit 10 receive from the user. Create layout data based on drawing commands. The created layout data is stored in the storage unit 13.

The layout data includes PCB information, component information, terminal information, net information, wiring information, design standard information, and the like.
The PCB information is information such as the configuration and dimensions of the PCB layer, and the electrical characteristics of the material constituting the PCB.
The component information includes a component number for identifying each component mounted on the PCB, a component shape for identifying the shape of the component, a component type for identifying the type of component, a component reference coordinate indicating the component arrangement position, and a component. This is information such as a component placement surface for identifying a surface and electrical characteristics of the component.

The terminal information is information such as a part number of a part to which the terminal belongs, a terminal number for identifying the terminal, and terminal coordinates indicating a terminal arrangement position.
The net information is information including a net name, a connection terminal number, and the like for identifying a connection relationship between terminals of each component.
The wiring information includes information for identifying whether the wiring is a surface or a line, the coordinates of the via, the wiring width, the wiring thickness, and, if the wiring is a line, the wiring start / end coordinates, the wiring layer, etc. When information is included and the wiring is a surface, information such as the number of constituent points, constituent point coordinates, and fill attributes is included.

The design standard information is information such as the thickness of the dielectric, the relative dielectric constant of the dielectric, the thickness of the conductive foil, and the clearance value.
The layout check unit 12 functions when the command input unit 10 receives a layout check command during the execution of the CAD application program, and the layout of the PCB defined by the layout data created by the layout data creation unit 11 is the PCB. A layout check process is performed to check whether the layout allows the bypass capacitor arranged above to function effectively.

In order to realize the layout check processing, the layout check unit 12 includes a data extraction unit 121, a calculation unit 122, a determination unit 123, and an error information output unit 124.
The data extraction unit 121 extracts various pieces of information necessary for performing the above-described check from the layout data stored in the storage unit 13, and combines a power supply pin and a bypass capacitor connected to the same power supply pattern. Identify. Details of various information will be described later.

The calculation unit 122 calculates a value Z1 corresponding to the impedance between the power supply pin of the high-speed IC and the power supply, and a value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor.
A value corresponding to the impedance will be described later.
The determination unit 123 compares the calculated values of Z1 and Z2, and determines that it is an error if Z1 is smaller than Z2.

  The error information output unit 124 checks all power supply pins and all bypass capacitors in the list information, and if there is an error determination in any combination of power supply pins and bypass capacitors, the checked layout is the bypass capacitor. Outputs error information indicating that the layout does not function effectively. The output error information is displayed on the display unit 14.

The storage unit 13 is a storage device such as a memory and a hard disk. Input circuit diagram data, created layout data, OS (Operating System), CAD application program, and the like are stored.
The display unit 14 is a display device and displays various types of information. For example, a layout diagram of the created PCB, error information output from the error information output unit 124, and the like are displayed.

<Example of PCB layout>
FIG. 2 is a diagram illustrating an example of a PCB layout that is a layout check target of the layout check process.
In the PCB layout of the figure, a high-speed IC 201, a bypass capacitor 202, a bypass capacitor 203, a bypass capacitor 204, and a bypass capacitor 205 are arranged on the surface layer. Although not shown, a power plane and a ground plane are arranged in the lower layer. ing.

In addition, the thick line drawn in the figure indicates the power supply pattern, the white circle indicates the power supply via or the power supply pattern existing in the lower layer, the hatched circle indicates the ground via connected to the ground plane existing in the lower layer, The dotted line graphic represents the power supply pattern 305 and the power supply via 3004 provided in the lower layer.
The high-speed IC 201 has various terminals in addition to a power supply pin 2001, a power supply pin 2002, a power supply pin 2003, and a ground pin 2004.

A power supply via 3001 provided in the power supply pattern 301 is connected to a power supply pattern 305 provided in a lower layer.
A power supply via 3002 provided in the power supply pattern 302, a power supply via 3003 provided in the power supply pattern 303, and a power supply via 3004 provided in the power supply pattern 305 are connected to a power supply plane provided in another layer.

Note that a part of the power supply pattern 302 and the power supply via 3002 are expressed through the high-speed IC 201, and the display of the control signal wiring pattern is omitted. Further, all the power supply patterns have the same width and thickness.
FIG. 3 is a diagram schematically showing a cross section when the PCB having the PCB layout shown in FIG. The figure shows that the ground via 3005 is connected to the ground plane 4001 and that the power supply via 3002 is connected to the power supply plane 4002.

FIG. 4 is a diagram illustrating an example of an equivalent circuit model of Z1 that is an impedance value between the power supply pin 2001 and the power supply 2000 and Z2 that is an impedance value between the power supply pin 2001 and the bypass capacitor 202.
Z1 and Z2 can be obtained from the capacitance c [F / m] and inductance l [H / m] per unit length of the power supply pattern, the distance between the power supply pin and the power supply, and the distance between the power supply pin and the bypass capacitor.

Here, a method for calculating the characteristic impedance of the microstripline structure and the power supply pattern of the stripline structure will be described.
In the case of the microstrip line structure, the unit length of the power supply pattern can be obtained by using information such as the width (w) of the power supply pattern, the thickness (h) of the dielectric, the relative dielectric constant (ε _r ) of the dielectric, and the following formula. Capacitance c [F / m], inductance l [H / m], and characteristic impedance Z [Ω] of the power supply pattern can be obtained.

If d <1,

Voは光速
また、ストリップライン構造の場合、電源パターンの幅（ｗ）、電源パターンの厚み（ｔ）、誘電体の厚み（Ｈ）、誘電体の比誘電率（ε_r）等の情報と下記の数式を用いることで、電源パターンの単位長あたりのキャパシタンスｃ[Ｆ／ｍ]及びインダクタンスｌ[Ｈ／ｍ]、そして、電源パターンの特性インピーダンスＺ[Ω]を求めることができる。 If d ≧ 1,

Vo is the speed of light. In the case of a stripline structure, information such as the width (w) of the power supply pattern, the thickness (t) of the power supply pattern, the thickness of the dielectric (H), the relative dielectric constant (ε _r ) of the dielectric and the following Is used, the capacitance c [F / m] and the inductance l [H / m] per unit length of the power supply pattern and the characteristic impedance Z [Ω] of the power supply pattern can be obtained.

Voは光速
＜動作＞
次に、レイアウトチェック部１２が行うレイアウトチェック処理について説明する。

Vo is the speed of light
Next, a layout check process performed by the layout check unit 12 will be described.

5 to 7 are flowcharts for explaining the layout check process according to the first embodiment.
First, in step S1, the data extraction unit 121 includes power pin list information including pin numbers, terminal coordinates, and net names of connection wirings for power pins to be checked, and part numbers, component coordinates, and connections for check target bypass capacitors. Bypass capacitor list information consisting of the net name of the wiring, net name for identifying the wiring, wiring type information for identifying whether the wiring is wiring of the line or wiring of the wiring, via coordinates indicating the position of the via provided in the wiring, wiring Wiring information including wiring width information indicating the width of the wiring, starting point coordinates indicating the starting point of the wiring, end point coordinates indicating the end point of the wiring, wiring hierarchy number indicating the substrate layer on which the wiring is provided, and the like is extracted from the storage unit 13.

In addition, when calculating the impedance value itself as Z1 and Z2, since it is necessary to calculate the characteristic impedance of the power supply pattern, the data extraction unit 121 is information indicating the wiring structure, and if the power supply pattern is a microstrip line structure Information on the dielectric thickness (h), relative dielectric constant (ε _r ) of the dielectric, etc., and stripline structure, it is necessary to extract information on the thickness (t) of the power supply pattern in addition to these information .

As the bypass capacitor, a capacitor connected to a power supply pattern and a ground pattern (a wiring pattern connected to the ground) is extracted from a large number of capacitors mounted on the PCB.
Next, pay attention to one power supply pin in the extracted power supply pin list information (step S2), and one bypass capacitor in the extracted bypass capacitor list information (step S3). It is determined whether or not the bypass capacitor is connected to the same power supply pattern (step S4). Such a determination is made by checking whether the net names are the same.

If the determination is affirmative (step S4: YES), the process proceeds to step S5. If the determination is negative (step S4: NO), the process proceeds to step S9.
In step S5, the calculation unit 122 calculates a value Z1 corresponding to the impedance between the power supply pin and the power supply, and subsequently calculates a value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor in step S6. Since the impedance on the power plane is very small, when a power plane is interposed between the power pin and the power source, a value corresponding to the impedance between power patterns connecting the power pin to the power plane is calculated as Z1.

The determination unit 123 compares Z1 and Z2 calculated by the calculation unit 122 (step S7). If Z1 is smaller than the value Z2 (step S7: YES), the determination unit 123 determines that there is an error (step S8). Thereafter, the process proceeds to step S9.
If Z1 is larger than Z2 (step S7: NO), the process proceeds to step S9.
When all the connection relationships between the noticed power supply pin and all bypass capacitors in the extracted bypass capacitor list information are checked (step S9: YES), the process proceeds to step S10, and otherwise (step S9: NO). Returning to step S3, attention is paid to another bypass capacitor.

In step S10, when all the power supply pins in the extracted power supply pin list information are checked (step S10: YES), the process proceeds to step S11. Otherwise (step S10: NO), the process returns to step S2. Focus on another power pin.
If at least one error is determined in step S8, error information indicating that the checked layout is not a layout that effectively functions the bypass capacitor is output (step S11), and the layout check process is terminated. To do.

<Specific example of layout check processing>
Here, the layout check process for the PCB layout shown in FIG. 2 will be described as an example of a specific layout check process.
As described above, since the width and thickness of all the power supply patterns on the PCB layout shown in FIG. 2 are the same, the impedance between the two points on the power supply pattern is a value proportional to the distance.

  When checking such a PCB layout, the layout check unit 12 calculates the shortest wiring distance between the power supply pin and the power supply as a value Z1 corresponding to the impedance between the power supply pin and the power supply, and the impedance between the power supply pin and the bypass capacitor. The shortest wiring distance between the power supply pin and the bypass capacitor is calculated as a value Z2 corresponding to, and these values are compared to determine whether the layout is an error.

Since the impedance of the power supply plane is very small, when the power supply plane is interposed between the power supply pin and the power supply, the distance of the power supply pattern connecting the power supply pin to the power supply plane is calculated as the shortest wiring distance between the power supply pin and the power supply.
First, various information extracted by the data extraction unit 121 will be described.
FIG. 8 is a diagram illustrating an example of the power pin list information extracted by the data extraction unit 121.

In the list information 800 shown in FIG. 8, the power supply pin number of each extracted power supply pin, the coordinates of the power supply pin, and the net name for identifying the wiring to which the power supply pin is connected are described.
FIG. 9 is a diagram illustrating an example of bypass capacitor list information extracted by the data extraction unit 121.
In the list information 900 shown in FIG. 9, the part number of each extracted bypass capacitor, the placement coordinates of the bypass capacitor, and the net name for identifying the wiring to which the bypass capacitor is connected are described.

FIG. 10 is a diagram illustrating an example of wiring information extracted by the data extraction unit 121.
The wiring information 1000 shown in the figure includes a wiring identification name for identifying a wiring, a net name for identifying a net, wiring type information for identifying whether the wiring is a wiring of a line or a surface, and a position of a via provided in the wiring. Information such as via coordinates to be shown, wiring width information to show the width of the wiring, starting point coordinates to show the starting point of the wiring, end coordinates to show the end point of the wiring, wiring layer number showing the substrate layer on which the wiring is provided, etc. .

The data extraction unit 121 extracts the various types of information shown in FIGS. 8 to 10 from the storage unit 13, and subsequently describes one of the power supply pins described in the list information 800 and the list information 900. Pay attention to one of the bypass capacitors, and check whether these are connected to the power supply pattern of the same net name.
Below, the calculation of Z1 and Z2 performed for the combination of the power supply pin and the bypass capacitor (the combination of (1) to (4)) connected to the power supply pattern of the same net name, and the calculated Z1 and Z2 A determination example based on a comparison between large and small will be described.
(1) In the case of the power supply pin 2001 and the bypass capacitor 202 connected to the power supply pattern 301 The calculation unit 122 calculates the shortest wiring distance L1 between the power supply pin 2001 and the power supply and the shortest wiring distance L2 between the power supply pin 2001 and the bypass capacitor 202. Is calculated based on the coordinate information.

L1 is a length obtained by adding the wiring distance l between the two points of the power supply pin 2001 and the power supply via 3001 on the power supply pattern 301 and the wiring distance m between the two points of the power supply via 3001 and the power supply via 3004 on the power supply pattern 305. It is.
The value of l is l = 101−99 = 2 from the terminal coordinates (99, 99) of the power supply pin 2001 and the via coordinates (101, 99) of the power supply via 3001.

The value of m is m = 107−99 = 8 from the via coordinates (101, 99) of the power supply via 3001 and the via coordinates (101, 107) of the power supply via 3004.
Therefore, L1 = l + m = 2 + 8 = 10.
The value of L2 is L2 = 105−99 = 6 from the terminal coordinates (99, 99) of the power supply pin 2001 and the component coordinates (105, 99) of the bypass capacitor.

The determination unit 123 compares Z1 and Z2 with L1 = Z1 = 10 and L2 = Z2 = 6, and does not determine an error because Z1 is larger than Z2.
(2) Case of Power Supply Pin 2002 Connected to Power Supply Pattern 302 and Bypass Capacitor 203 The calculation unit 122 calculates the shortest wiring distance L3 between the power supply pin 2002 and the power supply via 3002 and the shortest wiring between the power supply pin 2002 and the bypass capacitor 203. The distance L4 is calculated based on the coordinate information.

The value of L3 is L3 = 99−95 = 3 from the terminal coordinates (99, 93) of the power supply pin 2002 and the via coordinates (95, 93) of the power supply via 3002.
The value of L4 is L4 = 105−99 = 6 from the terminal coordinates (99, 93) of the power supply pin 2002 and the component coordinates (105, 93) of the bypass capacitor 203.
The determination unit 123 compares Z1 and Z2 with L3 = Z1 = 3 and L4 = Z2 = 6, and determines that an error occurs because Z1 is smaller than Z2.
(3) Case of Power Supply Pin 303 Connected to Power Supply Pattern 303 and Power Supply Pattern 304 and Bypass Capacitor 204 The calculation unit 122 calculates the shortest wiring distance L5 between the power supply pin 2003 and the power supply via 3003 and the power supply pin 2003 and the bypass capacitor 204. The shortest wiring distance L6 is calculated based on the coordinate information.

L5 is a length obtained by adding the wiring distance h from the start point to the end point of the power supply pattern 304 and the wiring distance i between the two points from the start point of the power supply pattern 303 to the power supply via 3003.
The value of h is h = 87−81 = 6 from the start point coordinates (97, 87) and end point coordinates (97, 81) of the power supply pattern 304.
The value of i is i = 100−97 = 3 from the start point coordinates (97, 81) of the power supply pattern 303 and the via coordinates (100, 81) of the power supply via 3003.

Therefore, L5 = h + i = 6 + 3 = 9.
The value of L6 is L6 = 87−80 = 7 from the terminal coordinates (97, 87) of the power supply pin 2003 and the component coordinates (97, 80) of the bypass capacitor 204.
The determination unit 123 compares Z1 and Z2 with L5 = Z1 = 9 and L6 = Z2 = 7, and does not determine that an error has occurred because Z1 is greater than Z2.
(4) Case of Power Supply Pattern 303 and Power Supply Pin 2003 Connected to Power Supply Pattern 304 and Bypass Capacitor 205 The calculation unit 122 calculates the shortest wiring distance L5 between the power supply pin 2003 and the power supply via 3003 and the power supply pin 2003 and the bypass capacitor 205. The shortest wiring distance L7 is calculated based on the coordinate information.

The value of L5 is as calculated previously, and L5 = 9.
The value of L7 is a length obtained by adding the wiring distance h from the start point to the end point of the power supply pattern 304 and the wiring distance j from the start point to the end point of the power supply pattern 303.
h is as previously calculated, and h = 6.
The value of j is j = 103−97 = 6 from the start point coordinates (97, 81) and end point coordinates (103, 81) of the power supply pattern 303.

Therefore, L7 = h + j = 6 + 6 = 12.
The determination unit 123 compares Z1 and Z2 with L5 = Z1 = 9 and L7 = Z2 = 12, and determines that an error occurs because Z1 is smaller than Z2.
<Modification>
The determination unit 123 of the layout check system 1 described above compares the value Z1 corresponding to the impedance between the power supply pin and the power supply and the value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor. The layout may be determined by comparing the ratio value with respect to Z2, that is, Z1 / Z2, and a threshold value.

FIG. 11 is a diagram illustrating an example of a graph of the impedance value Z1 between the power supply pin and the power supply and the impedance value Z2 between the power supply pin and the bypass capacitor that change according to the frequency.
The impedance of the power supply pattern and the bypass capacitor changes depending on the frequency. As shown in the figure, the magnitude relationship between Z1 and Z2 is reversed around 13 MHz, and at 32 MHz or higher, Z1 is one tenth or less of Z2.

FIG. 12 is obtained by adding a graph of Z1 / Z2 values and a threshold line to FIG.
When the specification defines that an error is detected when the value of Z1 / Z2 is 0.1 or less, the determination unit 123 determines that the value of Z1 / Z2 is 0.1 when the frequency is 32 MHz or more. Since it becomes the following, it determines with an error.
The determination may be made in consideration of the nth harmonic (n is a positive integer) of the fundamental frequency. In this case, at least the fifth harmonic should be taken into consideration. In the case of a circuit having a fundamental frequency of 10 MHz, the fifth harmonic is 50 MHz, and Z1 / Z2 <0.1 at 50 MHz. The checked layout is determined to be an error.
<Embodiment 2>
<Overview>
The layout check system of the second embodiment is obtained by adding a new function to the layout check unit 12 of the layout check system 1 described in the first embodiment, and is the same as that of the first embodiment except for the added function. It is.

The added functions are a function to determine whether the power supply pattern to which the power supply pin of the high-speed IC is connected is a power plane commonly called “power island”, and “power island” and main power supply This function analyzes whether or not there is a wiring that connects a plane (a plane directly connected to a power supply) without using a bypass capacitor.
In the conventional check system, the PCB layout with the “power island” enables the bypass capacitor placed around the “power island” to suppress unnecessary radiation noise from the high-speed IC connected to the “power island”. I didn't check if it had a layout that would work.

The layout check system according to the second embodiment is characterized by performing the following error determination using an additional function.
1. If the power supply pattern to which the power supply pin of the high-speed IC is connected is the main power supply plane, it is determined that an error has occurred.
2. If the power supply pattern to which the power supply pin of the high-speed IC is connected is “power island”, analyze whether there is a wiring that connects the “power island” and the main power plane without a bypass capacitor, If such a wiring exists, it is determined that an error has occurred.

<Configuration>
As described above, since the layout check system according to the second embodiment is different from the layout check system 1 according to the first embodiment only in the layout check unit, only the layout check unit that is different will be described.
FIG. 13 is a diagram illustrating a functional configuration of the layout check unit according to the second embodiment.

The layout check unit 12A includes a power island determination unit 125 and a connection information analysis unit 126 in addition to the data extraction unit 121, the calculation unit 122, the determination unit 123, and the error information output unit 124.
The connection information analysis unit 126 analyzes whether the power supply pattern to which the power supply pin noted in the data extraction unit 121 is connected is a surface wiring. In order to perform the analysis, the connection information analysis unit 126 refers to the wiring information.

When the power island determination unit 125 determines that the power pattern to which the noticed power pin is connected is “power island”, the connection information analysis unit 126 selects the “power island” and the main power plane. Whether or not there is a wiring to be connected without using a bypass capacitor is analyzed with reference to the wiring information, and if there is such a wiring as a result of the analysis, it is determined that there is an error.
When the connection information analysis unit 126 determines that the power pattern to which the noticed power supply pin is connected is a surface wiring, that is, a power plane, the power island determination unit 125 determines the size of the surface of the power plane. It is confirmed from the wiring information whether or not is below the threshold.

The power island determination unit 125 determines that it is a “power island” if the size of the surface of the power plane is equal to or smaller than the threshold, and determines that it is the main power plane if it is equal to or larger than the threshold. If the power supply pattern to which the noticed power supply pin is connected is the main power supply plane, it is determined that an error has occurred.
<Example of PCB layout>
FIG. 14 is a diagram illustrating an example of a PCB layout having a “power supply island”, which is a layout check target of the layout check process.

In the PCB layout of the figure, a high-speed IC 211, a bypass capacitor 206, a bypass capacitor 207, a bypass capacitor 208, and a bypass capacitor 209 are arranged on the surface layer, and a main power plane 1101 and a “power island” 1102 are shown in the lower layer. There is not a ground plane.
The thick line drawn in the figure represents the power supply pattern, the white circle represents the power supply via connected to the power supply plane existing in the other layer, and the hatched circle represents the ground via connected to the ground plane of the other layer.

The high-speed IC 211 has various terminals in addition to the power supply pin 2101, the power supply pin 2102, the power supply pin 2103, and the ground pin 2104.
The display of the control signal wiring pattern is omitted.
<Operation>
Next, a layout check process performed by the layout check unit 12A will be described.

FIG. 15 is a flowchart for explaining the layout check processing according to the second embodiment, and only the operation of a portion different from the layout check processing described in the first embodiment will be described.
The process is the same up to step S2 of the layout check process described in the first embodiment, and the process proceeds from step S2 to step S12 shown in FIG.

  In step S12, the connection information analysis unit 126 analyzes whether or not the power supply pattern to which the power supply pin noted in the data extraction unit 121 is connected is a surface wiring, and the power supply pattern is a surface wiring. (Step S12: YES), the process proceeds to Step S13. Otherwise (step S12: NO), the process proceeds to step S5 of the layout check process described in the first embodiment.

  In step S13, the power island determination unit 125 determines whether the size of the surface of the power pattern is equal to or smaller than the threshold value. If it is equal to or less than the threshold (step S13: YES), it is determined that the power pattern is “power island” (step S14). If not (step S13: NO), the power pattern is the main power plane. Determination is made (step S15).

If it is determined in step S14 that the power supply pattern is “power supply island”, the connection information analysis unit 126 determines whether or not there is a wiring that connects the “power supply island” and the main power supply plane without a bypass capacitor. Analysis is performed (step S16).
If there is a wiring that connects the “power island” and the main power plane without a bypass capacitor (step S16: YES), it is determined that there is an error (step S17), and there is no such wiring (step S16). S16: NO), the process proceeds to step S5.

If it is determined in step S15 that the power supply pattern is the main power supply plane, it is determined that there is an error (step S17), and the process proceeds to step S5.
When the layout check process is performed on the PCB layout shown in FIG. 11, the power supply pattern 351 that directly connects the “power supply island” 1102 and the main power supply pattern 1101 without using a bypass capacitor by the analysis performed by the connection information analysis unit 126 in step S <b> 16. Is detected, it is determined as an error.

Specifically, the analysis performed by the connection information analysis unit 126 includes “power island” 1102 and main power pattern graphic data (coordinate data representing a graphic) and coordinates of two power vias provided on the power pattern 351. , It is determined whether or not the coordinates of the two power supply vias are respectively located in the area indicated by the graphic data of “power supply island” 1102 and the area indicated by the graphic data of the main power supply pattern. Since the power supply pattern 351 corresponds to such a power supply pattern, it is determined as an error.
<Supplement>
Needless to say, the present invention is not limited to the above-described embodiments and modifications. The following cases are also included in the present invention.
(1) The layout check process described in the first embodiment is performed even when there is an error determination in the connection relationship between a certain power supply pin (referred to as the first power supply pin) and a certain bypass capacitor (referred to as the first bypass capacitor). The connection relationship between another power supply pin and the first bypass capacitor is checked. If it is determined that there is an error in the connection relationship between the first power supply pin and the first bypass capacitor, the first bypass capacitor is checked thereafter. The layout check process may be speeded up.
(2) In the first embodiment, the power supply pin of the component to be checked is described as the power supply pin of the high-speed IC. However, the power supply pin of the component specified by the connector or the user may be the check target.

In the first embodiment, the power supply pins to be checked and the bypass capacitors are combined and checked, but the user may specify the combination of the power supply pins and the bypass capacitors.
(3) The bypass capacitor to be checked may be divided into a high frequency bypass capacitor and a low frequency bypass capacitor in consideration of the impedance characteristics of the capacitor, and the check target may be selected and extracted.
(4) Although the error information is output to the display unit 14 in the first embodiment, the output destination may be the storage unit 13, and if the layout check system 1 is connected to the network, the output destination is selected. Other external devices connected to the network may be used.
(5) In the first embodiment, the wiring path distance between the power supply pin and the power supply via is compared as Z1, and the wiring distance between the power supply pin and the bypass capacitor is compared as Z2. If Z1 <Z2, it is determined as an error. May be determined to be an error when Z1 + α <Z2. In this case, the specific value α may be a value input by the user, or may be a specified value of the system.
(6) The present invention may be a layout check method including each procedure of the layout check process described above (the procedure shown in FIGS. 5, 6, 7, and 15), and the layout check process may be performed by a computer. It may be a program to be executed. Further, it may be a digital signal composed of the program.
(7) The present invention provides a computer-readable recording medium for the program or the digital signal, for example, a flexible disk, a hard disk, a CD-ROM, an MO, a DVD, a DVD-ROM, a DVD-RAM, a BD (Blu-ray Disc). ), Recorded in a semiconductor memory or the like.
(8) The present invention may transmit the program or the digital signal via a network such as an electric communication line, a wireless or wired communication line, or the Internet.
(9) The present invention is independent by transferring the program or the digital signal recorded on the recording medium, or transferring the control program or the digital signal via the network or the like. It may be implemented in the computer system.

  In the layout check system according to the present invention, the layout of the PCB defined by the layout data created by using a CAD system or the like is a layout that effectively functions the bypass capacitor disposed on the PCB. This is very useful because it can check more accurately than the conventional check system mentioned in the prior art.

1 is a diagram illustrating a functional configuration of a layout check system according to a first embodiment. It is a figure showing an example of the PCB layout for layout check. FIG. 3 is a diagram schematically showing a cross section when a PCB having the PCB layout shown in FIG. 2 is divided by a power supply pattern 302; It is a figure showing an example of the equivalent circuit of impedance value Z1 and impedance value Z2. FIG. 6 is a flowchart for explaining layout check processing according to the first embodiment. FIG. 6 is a flowchart for explaining layout check processing according to the first embodiment. FIG. 6 is a flowchart for explaining layout check processing according to the first embodiment. It is a figure which shows an example of the list information of the extracted power supply pin. It is a figure which shows an example of the list information of the extracted bypass capacitor. It is a figure which shows an example of wiring information. It is the figure which showed an example of the graph of the impedance value Z1 and the impedance value Z2 which change according to a frequency. It is the graph which added the graph of the value of Z1 / Z2 to FIG. FIG. 10 is a diagram illustrating a functional configuration of a layout check unit according to the second embodiment. It is the figure which showed an example of the PCB layout for layout check. FIG. 10 is a flowchart for explaining layout check processing according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Layout check system 9 Data input part 10 Command input part 11 Layout data creation part 12, 12A Layout check part 13 Storage part 14 Display part 121 Data extraction part 122 Calculation part 123 Determination part 124 Error information output part 125 Power supply island determination part 126 Connection information analyzer

Claims (3)

A layout check system for checking layout data defining a layout of a power supply on a printed circuit board, a component having a power supply pin, and a bypass capacitor,
The information including a basis for calculating a first value corresponding to an impedance between the power supply pin and the power supply and a second value corresponding to an impedance between the power supply pin and the bypass capacitor; Storage means for storing layout data;
Calculation means for calculating the first value and the second value based on the stored layout data;
A determination unit that compares the calculated first value and the second value to determine whether the layout is a layout that effectively functions the bypass capacitor;
If the negative determination is made by the determination means, e Bei and output means for outputting the error information,
The layout data includes wiring type information for identifying whether the wiring is a line or a surface, and for the wiring on the surface, size information indicating an area size is included,
The storage means stores a specified value,
The layout check system further includes:
Based on the wiring type information, analysis means for analyzing whether the wiring connecting the power supply pin and the capacitor is a surface wiring;
As a result of the analysis, when it is found that the wiring connecting the power supply pin and the capacitor is a surface wiring, referring to the size information, the area size of the wiring on the surface is stored as a specified value. A power plane determination means for determining whether or not the wiring of the surface is a specific power plane if it is equal to or less than a specified value,
When the power plane determination unit determines that the wiring on the surface connecting the power pin and the capacitor is a specific power plane, the analysis unit further includes the specific power plane based on the layout data. And the power supply are analyzed without being connected via the bypass capacitor, and as a result, it is found that the specific power supply plane and the power supply are connected via the bypass capacitor, the layout Determining that the layout does not function effectively for the bypass capacitor . The calculation means calculates a first value that is the shortest wiring distance between the power supply pin and the power supply and a second value that is the shortest wiring distance between the power supply pin and the bypass capacitor based on the layout data. ,
The said determination means determines that the said layout is not the layout which functions the said bypass capacitor effectively, if the said 1st value is smaller than the said 2nd value. Layout check system. When a power supply via is provided on the wiring connecting the power supply pin and the bypass capacitor,
The calculation means calculates a first value that is the shortest wiring distance between the power supply pin and the power supply via and a second value that is the shortest wiring distance between the power supply pin and the bypass capacitor based on the layout data. The layout check system according to claim 2, wherein:

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