JP2004192618A - Layout check system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout check system that accurately checks whether a PCB layout defined by layout data is one enabling effective functions of a bypass capacitor. <P>SOLUTION: The layout check system 1 comprises a data extraction part 121 for extracting, from layout data stored in a storage part 13, pieces of information fundamental to the calculation of a value Z1 corresponding to impedance between a power pin and a power source and a value Z2 corresponding to impedance between the power pin and a bypass capacitor, a calculation part 122 for calculating Z1 and Z2 according to the extracted pieces of information, a determination part 123 for comparing the calculated magnitudes of Z1 and Z2 to determine whether the layout is one enabling effective functions of the bypass capacitor, and an error information output part 124 for outputting error information if the determination part 123 produces a negative determination. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a CAD (Computer Aided Design) technique used for a layout design of a printed wiring board (hereinafter, referred to as a PCB), and particularly to a PCB defined by layout data created using a CAD system. The present invention relates to a technique for checking whether a layout is a layout that allows a bypass capacitor arranged on a PCB to function effectively.

2. Description of the Related Art In recent years, with the advancement of performance and digitalization of electronic devices, high-speed digital ICs (hereinafter, referred to as high-speed ICs) that perform high-speed switching operations have been used as main components of electronic devices.
High-speed ICs generate high-frequency fluctuations in the power supply voltage by performing high-speed switching operations, and emit unnecessary radiation noise. Therefore, it is common to arrange a bypass capacitor near a power supply pin of a high-speed IC on a PCB on which the high-speed IC is mounted.

By arranging the bypass capacitor at an appropriate position, the high-frequency fluctuation of the power supply voltage generated by the high-speed switching operation of the high-speed IC is compensated and stabilized by the electric charge stored in the bypass capacitor, and the high-frequency component of the high-speed IC is reduced. The effect is obtained that the unnecessary radiation noise can be confined around the high-speed IC by returning to the GND pin.
A layout such as an arrangement of various components mounted on a PCB and a wiring pattern is generally defined by layout data created by a layout designer using a CAD system. In creating the layout data, a layout error in which the bypass capacitor does not function effectively may occur.

As a technique for checking whether there is such a layout error, there is a "printed wiring structure check system (hereinafter simply referred to as a check system)" disclosed in the following patent document.
This check system, when the wiring structure of the temporarily designed wiring on the printed circuit board meets one of several error conditions prepared in advance, namely, the condition that the bypass capacitor does not function effectively, It is characterized by displaying a countermeasure instruction for the error (hereinafter, referred to as an error countermeasure instruction) as an error.

For example, when one bypass capacitor is arranged so as to correspond to a predetermined number or more of the power pins of the high-speed IC, or when a via exists between the wiring path of the bypass capacitor and the power pin of the high-speed IC, an error countermeasure instruction is issued. Is displayed.
JP-A-2002-16337

However, there are some error conditions that cannot be checked by the above check system.
For example, when a power supply via exists on a wiring to which the power supply pin is connected other than between the wiring path of the power supply pin of the high-speed IC and the bypass capacitor, the bypass capacitor may not function effectively.

  In order for the bypass capacitor to function effectively, the impedance between the power supply pin and the wiring path of the bypass capacitor must be smaller than the impedance between the power supply pin and the wiring path of the power supply so that high-frequency current flows to the bypass capacitor. However, if the wiring distance between the power supply via and the power supply pin is shorter than the wiring distance between the power supply pin and the bypass capacitor, the impedance between the power supply pin and the power supply will be smaller than the impedance between the power supply pin and the bypass capacitor. The bypass capacitor may not be able to function effectively.

The above-described checking system only checks whether or not a via exists between the wiring paths between the bypass capacitor and the power supply pin of the high-speed IC, and therefore cannot check for such an error condition.
In the above-described check system, an error countermeasure instruction is displayed when a via exists between the path of the power supply pattern to which the bypass capacitor and the power supply pin of the high-speed IC are connected. However, this is not necessarily an error. There are cases.

  If it is assumed that the connection destination of the via is always the power plane, it may be determined that there is an error, but if the connection destination of the via is not the power plane but the power supply pattern of the line wiring, the power supply of the connection destination It is necessary to consider the impedance between the wirings to the power supply of the pattern. In this case, since the impedance between the power supply pin and the power supply may be larger than the impedance between the power supply pin and the bypass capacitor, it is erroneous to determine that an error is necessarily generated.

  The present invention relates to a layout check system and a system capable of checking whether or not a layout of a PCB is a layout that allows a bypass capacitor arranged on the PCB to function effectively, more accurately than a conventional check system. The purpose is to provide various technologies.

  To achieve the above object, a layout check system according to the present invention is a layout check system that checks layout data defining a layout of a power supply on a printed wiring board, a component having a power supply pin, and a bypass capacitor, The information including a base value for calculating a first value that is a value corresponding to the impedance between the power supply pin and the power supply and a second value that is a value corresponding to the impedance between the power supply pin and the bypass capacitor. Storage means for storing layout data; calculating means for calculating the first value and the second value based on the stored layout data; and calculating the first value and the second value. Comparing the magnitudes of the values of Determination means for determining whether a bets, if a negative determination is made by the determination unit, and an outputting means for outputting the error information.

  The layout check method according to the present invention is a layout check method for checking layout data defining a layout of a power supply on a printed circuit board, a component having a power supply pin, and a bypass capacitor, wherein the power supply pin and the Layout data including information serving as a basis for calculating a first value corresponding to an impedance between power supplies and a second value corresponding to an impedance between the power supply pin and the bypass capacitor is obtained. An obtaining step, a calculating step of calculating the first value and the second value based on the layout data, and comparing the calculated first value and the magnitude of the second value. To determine whether the layout is a layout that allows the bypass capacitor to function effectively. If the determination step, the negative determination in said determination step is performed, characterized in that it comprises an output step of outputting the error information.

  The program according to the present invention is a program for causing a computer to perform a layout check process for checking layout data defining a layout of a power supply on a printed wiring board, a component having a power supply pin, and a bypass capacitor. The layout check process is based on calculating a first value that is a value corresponding to the impedance between the power supply pin and the power supply and a second value that is a value corresponding to the impedance between the power supply pin and the bypass capacitor. Obtaining layout data including the following information: calculating the first value and the second value based on the layout data; calculating the first value and the second value based on the calculated first value and the second value The layout enables the bypass capacitor by comparing the magnitudes of the values of If a judgment step of judging whether a layout to ability, negative determination in said determination step is performed, characterized in that it comprises an output step of outputting the error information.

  Here, the value corresponding to the impedance refers to, for example, a wiring distance that is proportional to the magnitude of the impedance of the wiring, in addition to the value of the impedance itself.

  The layout check system, the layout check method, and the program having the above-described configuration include a first value that is a value corresponding to an impedance between a power supply pin and a power supply, and a second value that is a value corresponding to an impedance between the power supply pin and a bypass capacitor. By calculating and comparing, it is determined whether or not the checked layout is a layout that allows the bypass capacitor to function effectively, so that a more accurate error determination can be made than the checking system described in the above-mentioned publication.

  In addition, the calculating unit calculates a first value that is a shortest wiring distance between the power supply pin and the power supply and a second value that is a shortest wiring distance between the power supply pin and the bypass capacitor based on the layout data. When calculating, the determination unit may determine that the layout is not a layout that allows the bypass capacitor to function effectively if the first value is smaller than the second value.

With this configuration, when the magnitude of the impedance between the two points on the wiring is proportional to the distance, the shortest wiring distance between the power supply pin and the power supply and the power supply pin and the bypass capacitor can be calculated without calculating the impedance value. By calculating the shortest wiring distance between them and comparing these sizes, it can be determined whether the checked layout is an error.
In the case where a power supply via is provided on a wiring connecting the power supply pin and the bypass capacitor, the calculating unit calculates a shortest wiring distance between the power supply pin and the power supply via based on the layout data. A certain first value and a second value that is the shortest wiring distance between the power supply pin and the bypass capacitor may be calculated.

  According to this configuration, when the connection destination of the power supply via is a power supply plane and the impedance of the power supply plane is regarded as 0, the shortest wiring distance between the power supply pin and the power supply via and the power supply plane can be calculated without calculating the impedance value. By calculating the shortest wiring distance between the pin and the bypass capacitor and comparing these sizes, it can be determined whether or not the checked layout is an error.

In addition, the storage unit stores a threshold value, and the determination unit compares the stored threshold value with a value of a ratio of the second value to the first value, and It may be determined whether or not the layout is a layout that allows the bypass capacitor to function effectively.
Further, the layout data includes wiring type information for identifying whether the wiring is a line or a surface, and for a surface wiring, size information indicating an area size is included, and the storage unit stores a specified value. The layout check system further includes an analysis unit configured to analyze whether the wiring connecting the power supply pin and the capacitor is a surface wiring based on the wiring type information, and a result of the analysis, When it is determined that the wiring connecting the power supply pin and the capacitor is a surface wiring, referring to the size information, it is determined whether or not the area size of the wiring on the surface is equal to or less than a stored specified value. Power supply plane determining means for determining that the wiring on the surface is a specific power supply plane when the value is equal to or less than a specified value. If it is determined that the wiring on the surface connecting the capacitor and the capacitor is the specific power plane, the analysis unit further includes the specific power plane and the power supply via the bypass capacitor based on the layout data. If the specific power supply plane and the power supply are found to be connected without passing through the bypass capacitor, the layout makes the bypass capacitor function effectively. The layout may not be determined.

  With this configuration, it is possible to check whether the layout is such that unnecessary radiation noise generated from the power supply pins connected to the specific power supply plane does not leak out of the specific power supply plane.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment described below is an example embodying the present invention, and does not limit the technical scope of the present invention.
<Embodiment 1>
<Overview>
The layout check system according to the first embodiment is a CAD system used for a layout design of a PCB, and a layout designer creates layout data using the present system.

  A feature of the layout check system of the present embodiment is to check whether or not the layout of the PCB defined by the created layout data is a layout for effectively functioning the bypass capacitors arranged on the PCB. Then, a value Z1 corresponding to the impedance between the power supply pin and the power supply of the high-speed IC arranged on the PCB and a value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor are calculated, and the calculated two values are compared. , Z1 is smaller than Z2, an error is determined, and error information is output.

<Structure>
FIG. 1 is a diagram illustrating a functional configuration of the layout check system according to the first embodiment.
The layout check system 1 includes functional units such as a data input unit 9, a command input unit 10, a layout data creation unit 11, a layout check unit 12, a storage unit 13, and a display unit 14. Note that descriptions of functions that are not necessary for describing the features of the present invention are omitted.

The layout check system 1 is a computer including hardware such as a CPU, an input device, an output device, and a storage device. The CPU executes a program stored in the storage device to realize each function.
The data input unit 9 receives input of circuit diagram data created using a circuit diagram design CAD device or the like. The received circuit diagram data is stored in the storage unit 13.

  The command input unit 10 receives a command input by a user operating an input device such as a keyboard and a mouse. The commands include, for example, a start command for starting a CAD application program, a drawing command for deciding the arrangement and wiring pattern of components on a PCB layout diagram, and a layout check command for checking a created layout.

  The layout data creation unit 11 functions when the command input unit 10 receives a start command from the user and starts the CAD application program. The input circuit diagram data and the command input unit 10 receive the input from the user. Create layout data based on drawing commands. The created layout data is stored in the storage unit 13.

The layout data includes PCB information, component information, terminal information, net information, wiring information, design reference information, and the like.
The PCB information is information such as the configuration and dimensions of the layers of the PCB, and the electrical characteristics of the materials constituting the PCB.
The component information includes a component number for identifying each component mounted on the PCB, a component shape for identifying a component shape, a component type for identifying a component type, component reference coordinates indicating a component placement position, and components. Information such as a component placement surface for identifying a surface and electrical characteristics of the component.

The terminal information is information such as a part number of a part to which the terminal belongs, a terminal number for identifying the terminal, and terminal coordinates indicating a terminal arrangement position.
The net information is information including a net name for identifying a connection relationship between terminals of each component, a connection terminal number, and the like.
The wiring information includes information for identifying whether the wiring is a surface or a line, coordinates of vias, width of the wiring, thickness of the wiring, start / end coordinates of the wiring when the wiring is a line, wiring layers and the like. When the wiring is a plane, the information includes information such as the number of constituent points, the coordinates of the constituent points, and the paint attribute.

The design reference information is information such as the thickness of the dielectric, the relative permittivity of the dielectric, the thickness of the conductive foil, and the clearance value.
The layout check unit 12 functions when the command input unit 10 receives a layout check command during execution of the CAD application program, and the layout of the PCB defined by the layout data created by the layout data creation unit 11 A layout check process is performed to check whether the layout is such that the bypass capacitor disposed above functions effectively.

To realize such a layout check process, the layout check unit 12 includes a data extraction unit 121, a calculation unit 122, a determination unit 123, and an error information output unit 124.
The data extraction unit 121 extracts various pieces of information necessary for performing the above-described check from the layout data stored in the storage unit 13 and determines a combination of a power supply pin and a bypass capacitor connected to the same power supply pattern. Identify. Details of various information will be described later.

The calculation unit 122 calculates a value Z1 corresponding to the impedance between the power supply pin of the high-speed IC and the power supply, and a value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor.
The value corresponding to the impedance will be described later.
The determination unit 123 compares the calculated magnitudes of Z1 and Z2, and determines that an error has occurred if Z1 is smaller than Z2.

  The error information output unit 124 checks all power supply pins and all bypass capacitors in the list information, and if an error is determined in any combination of power supply pins and bypass capacitors, the checked layout is a bypass capacitor. Error information indicating that the layout does not function effectively. The output error information is displayed on the display unit 14.

The storage unit 13 is a storage device such as a memory and a hard disk. It stores input circuit diagram data, created layout data, an OS (Operating System), a CAD application program, and the like.
The display unit 14 is a display device and displays various information. For example, a layout diagram of the created PCB, error information output from the error information output unit 124, and the like are displayed.

<Example of PCB layout>
FIG. 2 is a diagram illustrating an example of a PCB layout to be subjected to a layout check in the layout check process.
In the PCB layout shown in the figure, a high-speed IC 201, a bypass capacitor 202, a bypass capacitor 203, a bypass capacitor 204, and a bypass capacitor 205 are arranged on a surface layer. Although not shown, a power plane and a ground plane are arranged in a lower layer. ing.

Also, the thick line drawn in the figure is a power supply pattern, a white circle is a power supply via connected to a power supply plane or a power supply pattern present in a lower layer, a hatched circle is a ground via connected to a ground plane present in a lower layer, The dotted lines indicate the power supply pattern 305 and the power supply via 3004 provided in the lower layer.
The high-speed IC 201 has various terminals in addition to a power pin 2001, a power pin 2002, a power pin 2003, and a ground pin 2004.

A power supply via 3001 provided in the power supply pattern 301 is connected to a power supply pattern 305 provided in a lower layer.
A power supply via 3002 provided in the power supply pattern 302, a power supply via 3003 provided in the power supply pattern 303, and a power supply via 3004 provided in the power supply pattern 305 are connected to a power supply plane provided in another layer.

Note that a part of the power supply pattern 302 and the power supply via 3002 are expressed in a form that allows the high-speed IC 201 to pass through, and the display of the control signal wiring pattern is omitted. The width and thickness of all power supply patterns are the same.
FIG. 3 is a diagram schematically illustrating a cross section when the PCB of the PCB layout illustrated in FIG. 2 is divided by the power supply pattern 302. This figure shows that the ground via 3005 is connected to the ground plane 4001 and that the power supply via 3002 is connected to the power plane 4002.

FIG. 4 is a diagram illustrating an example of an equivalent circuit model of Z1 which is an impedance value between the power supply pin 2001 and the power supply 2000 and Z2 which is an impedance value between the power supply pin 2001 and the bypass capacitor 202.
Z1 and Z2 can be determined from the capacitance c [F / m] and inductance l [H / m] per unit length of the power supply pattern, the distance between the power supply pin and the power supply, and the distance between the power supply pin and the bypass capacitor.

Here, a method of calculating the characteristic impedance of the power supply pattern having the microstrip line structure and the strip line structure will be described.
In the case of the microstrip line structure, the unit length of the power supply pattern is obtained by using information such as the width (w) of the power supply pattern, the thickness (h) of the dielectric, the relative permittivity (ε _r ) of the dielectric, and the following formula. The capacitance c [F / m] and the inductance l [H / m] per unit, and the characteristic impedance Z [Ω] of the power supply pattern can be obtained.

If d <1,

Voは光速
また、ストリップライン構造の場合、電源パターンの幅（ｗ）、電源パターンの厚み（ｔ）、誘電体の厚み（Ｈ）、誘電体の比誘電率（ε_r）等の情報と下記の数式を用いることで、電源パターンの単位長あたりのキャパシタンスｃ[Ｆ／ｍ]及びインダクタンスｌ[Ｈ／ｍ]、そして、電源パターンの特性インピーダンスＺ[Ω]を求めることができる。 When d ≧ 1,

Vo is the speed of light. In the case of a stripline structure, information such as the width (w) of the power supply pattern, the thickness (t) of the power supply pattern, the thickness (H) of the dielectric, and the relative permittivity (ε _r ) of the dielectric are shown below. By using the mathematical formula, the capacitance c [F / m] and the inductance l [H / m] per unit length of the power supply pattern, and the characteristic impedance Z [Ω] of the power supply pattern can be obtained.

Voは光速
＜動作＞
次に、レイアウトチェック部１２が行うレイアウトチェック処理について説明する。

Vo is the speed of light <Operation>
Next, a layout check process performed by the layout check unit 12 will be described.

FIG. 5 to FIG. 7 are flowcharts for explaining the layout check processing according to the first embodiment.
First, in step S1, the data extraction unit 121 checks the power supply pin list information including the pin number, the terminal coordinates, and the net name of the connection wiring for the power supply pin to be checked, and the component number, component coordinates, and connection for the bypass capacitor to be checked. Bypass capacitor list information including the net name of the wiring, net name for identifying the wiring, wiring type information for identifying whether the wiring is a wiring of a line or a surface wiring, via coordinates indicating the position of a via provided in the wiring, wiring The storage unit 13 extracts wiring information including wiring width information indicating the width of the wiring, starting point coordinates indicating the starting point of the wiring, end point coordinates indicating the ending point of the wiring, a wiring layer number indicating the substrate layer on which the wiring is provided, and the like.

Note that when calculating the impedance value itself as Z1 and Z2, it is necessary to calculate the characteristic impedance of the power supply pattern. Therefore, the data extraction unit 121 provides information indicating the wiring structure, if the power supply pattern is a microstrip line structure. , The dielectric thickness (h), the relative permittivity (ε _r ) of the dielectric, and the like, and in the case of a stripline structure, it is necessary to extract information on the thickness (t) of the power supply pattern, etc. .

The bypass capacitor extracts a capacitor connected to a power supply pattern and a ground pattern (a wiring pattern connected to the ground) from among many capacitors mounted on the PCB.
Next, one power pin in the extracted power pin list information (step S2) and one bypass capacitor in the extracted bypass capacitor list information are focused (step S3). It is determined whether or not the bypass capacitors are connected to the same power supply pattern (step S4). Such determination is made by checking whether the net names are the same.

If the determination is affirmative (step S4: YES), the process proceeds to step S5, and if the determination is negative (step S4: NO), the process proceeds to step S9.
In step S5, the calculation unit 122 calculates a value Z1 corresponding to the impedance between the power supply pin and the power supply, and subsequently, in step S6, calculates a value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor. Since the impedance on the power supply plane is very small, when a power supply plane is interposed between the power supply pin and the power supply, a value corresponding to the impedance between the power supply patterns connecting the power supply pin to the power supply plane is calculated as Z1.

The determination unit 123 compares Z1 and Z2 calculated by the calculation unit 122 (step S7), and if Z1 is smaller than the value Z2 (step S7: YES), determines that there is an error (step S8). Thereafter, the process proceeds to step S9.
If Z1 is larger than Z2 (step S7: NO), the process proceeds to step S9.
If all the connection relations between the noted power supply pin and all the bypass capacitors in the extracted bypass capacitor list information have been checked (step S9: YES), the process proceeds to step S10, otherwise (step S9: NO). Returning to step S3, attention is paid to another bypass capacitor.

In step S10, if all the power pins in the extracted power pin list information have been checked (step S10: YES), the process proceeds to step S11; otherwise (step S10: NO), the process returns to step S2. Look at another power pin.
If any error is determined in step S8, error information indicating that the checked layout is not a layout for effectively functioning the bypass capacitor is output (step S11), and the layout check processing ends. I do.

<Specific example of layout check processing>
Here, a layout check process of the PCB layout shown in FIG. 2 will be described as an example of a specific layout check process.
As described above, since the width and thickness of all power supply patterns on the PCB layout shown in FIG. 2 are the same, the impedance between two points on the power supply pattern has a value proportional to the distance.

  When checking such a PCB layout, the layout check unit 12 calculates the shortest wiring distance between the power supply pin and the power supply as a value Z1 corresponding to the impedance between the power supply pin and the power supply, and calculates the impedance between the power supply pin and the bypass capacitor. , The shortest wiring distance between the power supply pin and the bypass capacitor is calculated, and these values are compared to determine whether the layout has an error.

Since the impedance of the power supply plane is very small, when a power supply plane is interposed between the power supply pin and the power supply, the distance of the power supply pattern connecting the power supply pin to the power supply plane is calculated as the shortest wiring distance between the power supply pin and the power supply.
First, various information extracted by the data extraction unit 121 will be described.
FIG. 8 is a diagram illustrating an example of the power pin list information extracted by the data extracting unit 121.

In the list information 800 shown in FIG. 8, the extracted power supply pin number of each power supply pin, the coordinates of the power supply pin, and the net name for identifying the wiring connected to the power supply pin are described.
FIG. 9 is a diagram illustrating an example of list information of bypass capacitors extracted by the data extraction unit 121.
The list information 900 shown in FIG. 9 describes the extracted component number of each bypass capacitor, the arrangement coordinates of the bypass capacitor, and the net name for identifying the wiring connected to the bypass capacitor.

FIG. 10 is a diagram illustrating an example of the wiring information extracted by the data extraction unit 121.
The wiring information 1000 of FIG. 3 includes a wiring identifier for identifying the wiring, a net name for identifying the net, wiring type information for identifying whether the wiring is a wiring of a line or a surface wiring, and a position of a via provided in the wiring. Information such as via coordinates indicating the wiring, wiring width information indicating the width of the wiring, start coordinates indicating the starting point of the wiring, end coordinates indicating the ending point of the wiring, and a wiring layer number indicating the substrate layer on which the wiring is provided are described. .

The data extraction unit 121 extracts the various information shown in FIGS. 8 to 10 from the storage unit 13, and then extracts one of the power supply pins described in the list information 800 and the information described in the list information 900. Attention is paid to one of the bypass capacitors, and it is confirmed whether or not these are connected to the power supply pattern having the same net name.
In the following, calculation of Z1 and Z2 performed on the combination of the power supply pin and the bypass capacitor (combination of (1) to (4)) connected to the power supply pattern of the same net name and calculation of the calculated Z1 and Z2 are performed. A description will be given of an example of determination based on comparison of magnitude.
(1) In the case of the power supply pin 2001 and the bypass capacitor 202 connected to the power supply pattern 301, the calculation unit 122 calculates the shortest wiring distance L1 between the power supply pin 2001 and the power supply and the shortest wiring distance L2 between the power supply pin 2001 and the bypass capacitor 202. Is calculated based on the coordinate information.

L1 is a length obtained by adding a wiring distance 1 between two points of the power supply pin 2001 and the power supply via 3001 on the power supply pattern 301 and a wiring distance m between two points of the power supply via 3001 and the power supply via 3004 on the power supply pattern 305. It is.
The value of 1 is 1 = 101−99 = 2 from the terminal coordinates (99, 99) of the power supply pin 2001 and the via coordinates (101, 99) of the power supply via 3001.

Further, the value of m is m = 107−99 = 8 from the via coordinates (101, 99) of the power supply via 3001 and the via coordinates (101, 107) of the power supply via 3004.
Therefore, L1 = l + m = 2 + 8 = 10.
Further, the value of L2 is L2 = 105−99 = 6 based on the terminal coordinates (99, 99) of the power supply pin 2001 and the component coordinates (105, 99) of the bypass capacitor.

The determination unit 123 compares L1 = Z1 = 10 and L2 = Z2 = 6 to compare the magnitudes of Z1 and Z2. Since Z1 is larger than Z2, it does not determine an error.
(2) In the case of the power supply pin 2002 and the bypass capacitor 203 connected to the power supply pattern 302, the calculation unit 122 calculates the shortest wiring distance L3 between the power supply pin 2002 and the power supply via 3002 and the shortest wiring between the power supply pin 2002 and the bypass capacitor 203. The distance L4 is calculated based on the coordinate information.

The value of L3 is L3 = 99−95 = 3 from the terminal coordinates (99, 93) of the power supply pin 2002 and the via coordinates (95, 93) of the power supply via 3002.
The value of L4 is L4 = 105−99 = 6 from the terminal coordinates (99, 93) of the power supply pin 2002 and the component coordinates (105, 93) of the bypass capacitor 203.
The determination unit 123 compares L1 = Z1 = 3 and L4 = Z2 = 6, compares Z1 with Z2, and determines that an error has occurred because Z1 is smaller than Z2.
(3) In the case of the power supply pin 2003 and the bypass capacitor 204 connected to the power supply pattern 303 and the power supply pattern 304, the calculation unit 122 calculates the shortest wiring distance L5 between the power supply pin 2003 and the power supply via 3003 and the power supply pin 2003 and the bypass capacitor 204 The shortest wiring distance L6 between them is calculated based on the coordinate information.

L5 is the length obtained by adding the wiring distance h from the start point to the end point of the power supply pattern 304 and the wiring distance i between the two points from the start point of the power supply pattern 303 to the power supply via 3003.
The value of h is h = 87−81 = 6 from the start point coordinates (97, 87) and end point coordinates (97, 81) of the power supply pattern 304.
The value of i is i = 100−97 = 3 from the start point coordinates (97, 81) of the power supply pattern 303 and the via coordinates (100, 81) of the power supply via 3003.

Therefore, L5 = h + i = 6 + 3 = 9.
From the terminal coordinates (97, 87) of the power supply pin 2003 and the component coordinates (97, 80) of the bypass capacitor 204, the value of L6 is L6 = 87-80 = 7.
The determination unit 123 compares L1 with Z2 by setting L5 = Z1 = 9 and L6 = Z2 = 7, and does not determine an error because Z1 is larger than Z2.
(4) In the case of the power supply pin 2003 and the bypass capacitor 205 connected to the power supply pattern 303 and the power supply pattern 304, the calculation unit 122 calculates the shortest wiring distance L5 between the power supply pin 2003 and the power supply via 3003 and the power supply pin 2003 and the bypass capacitor 205 The shortest wiring distance L7 between them is calculated based on the coordinate information.

The value of L5 is as previously calculated, and L5 = 9.
The value of L7 is a length obtained by adding the wiring distance h from the start point to the end point of the power supply pattern 304 and the wiring distance j from the start point to the end point of the power supply pattern 303.
h is as previously calculated, and h = 6.
The value of j is j = 103−97 = 6 from the start point coordinates (97, 81) and end point coordinates (103, 81) of the power supply pattern 303.

Therefore, L7 = h + j = 6 + 6 = 12.
The determination unit 123 compares L1 and Z2 with L5 = Z1 = 9 and L7 = Z2 = 12, and determines that an error has occurred because Z1 is smaller than Z2.
<Modification>
The determination unit 123 of the above-described layout check system 1 compares the value Z1 corresponding to the impedance between the power supply pin and the power supply with the value Z2 corresponding to the impedance between the power supply pin and the bypass capacitor. The layout may be determined by comparing a ratio value to Z2, that is, Z1 / Z2, with a threshold value.

FIG. 11 is a diagram illustrating an example of a graph of the impedance value Z1 between the power supply pin and the power supply and the impedance value Z2 between the power supply pin and the bypass capacitor that change according to the frequency.
The power supply pattern and the impedance of the bypass capacitor change according to the frequency. As shown in the drawing, the magnitude relationship between Z1 and Z2 is reversed around 13 MHz, and above 32 MHz, Z1 is less than 1/10 of Z2.

FIG. 12 is obtained by adding a graph of Z1 / Z2 values and a threshold line to FIG.
When the value of Z1 / Z2 is equal to or less than 0.1 and the specification specifies that an error is to be determined, the determination unit 123 determines that the value of Z1 / Z2 is 0.1 if the frequency is 32 MHz or more. It is determined as an error because of the following.
Alternatively, the determination may be made in consideration of up to the nth harmonic (n is a positive integer) of the fundamental frequency. In this case, at least the fifth harmonic should be considered. In the case of a circuit having a fundamental frequency of 10 MHz, the fifth harmonic is 50 MHz, and at 50 MHz, Z1 / Z2 <0.1. The checked layout is determined to be an error.
<Embodiment 2>
<Overview>
The layout check system according to the second embodiment is obtained by adding a new function to the layout check unit 12 of the layout check system 1 described in the first embodiment, and is similar to the first embodiment except for the added function. It is.

The added functions are a function to determine whether the power supply pattern to which the power supply pin of the high-speed IC is connected is a power supply plane commonly called a “power supply island”, and a function to determine whether the power supply island is a main power supply. This function analyzes whether there is a wiring that connects a plane (plane directly connected to a power supply) without using a bypass capacitor.
In the conventional check system, the PCB layout with the "power island" uses a bypass capacitor placed around the "power island" to suppress unnecessary radiation noise generated from the high-speed IC connected to the "power island". I didn't check if the layout worked.

The layout check system according to the second embodiment is characterized in that the following error determination is performed by using an additional function.
1. If the power supply pattern to which the power supply pin of the high-speed IC is connected is the main power supply plane, it is determined that an error has occurred.
2. If the power supply pattern to which the power supply pin of the high-speed IC is connected is a "power supply island", analyze whether there is a wiring connecting the "power supply island" and the main power supply plane without using a bypass capacitor, If such a wiring exists, it is determined that an error has occurred.

<Structure>
As described above, the layout check system according to the second embodiment differs from the layout check system 1 according to the first embodiment only in the layout check unit. Therefore, only the layout check unit that is different will be described.
FIG. 13 is a diagram illustrating a functional configuration of a layout check unit according to the second embodiment.

The layout check unit 12A includes a power supply island determination unit 125 and a connection information analysis unit 126 in addition to the data extraction unit 121, the calculation unit 122, the determination unit 123, and the error information output unit 124.
The connection information analysis unit 126 analyzes whether the power supply pattern to which the power supply pin of interest in the data extraction unit 121 is connected is a surface wiring. In order to perform such analysis, the connection information analysis unit 126 refers to the wiring information.

When the power supply island determination unit 125 determines that the power supply pattern to which the power supply pin of interest is connected is “power supply island”, the connection information analysis unit 126 sets “power supply island” and the main power supply plane to “power supply island”. An analysis is performed with reference to the wiring information to determine whether there is a wiring to be connected without passing through the bypass capacitor. As a result of the analysis, if there is such a wiring, it is determined that an error has occurred.
When the connection information analysis unit 126 determines that the power supply pattern to which the target power pin is connected is a surface wiring, that is, a power supply plane, the power supply island determination unit 125 determines the size of the surface of the power supply plane. Is checked from the wiring information as to whether or not is less than the threshold.

If the size of the plane of the power plane is equal to or smaller than the threshold, the power island determining unit 125 determines that the power plane is a “power island”. If the power supply pattern to which the power supply pin of interest is connected is the main power supply plane, it is determined that an error has occurred.
<Example of PCB layout>
FIG. 14 is a diagram illustrating an example of a PCB layout having a “power island”, which is a layout check target of the layout check process.

In the PCB layout of the figure, a high-speed IC 211, a bypass capacitor 206, a bypass capacitor 207, a bypass capacitor 208, and a bypass capacitor 209 are arranged on a surface layer, and a main power plane 1101 and a "power island" 1102 are shown in a lower layer. Not, but a ground plane is located.
The thick line in the drawing indicates a power supply pattern, a white circle indicates a power supply via connected to a power supply plane existing in another layer, and a hatched circle indicates a ground via connected to a ground plane in another layer.

The high-speed IC 211 has a power supply pin 2101, a power supply pin 2102, a power supply pin 2103, a ground pin 2104, and various terminals.
The display of the control signal wiring pattern is omitted.
<Operation>
Next, a layout check process performed by the layout check unit 12A will be described.

FIG. 15 is a flowchart for explaining the layout check processing according to the second embodiment. Only the operation of a portion different from the layout check processing described in the first embodiment will be described.
Step S2 of the layout check process described in the first embodiment is the same, and the process proceeds from step S2 to step S12 shown in FIG.

  In step S12, the connection information analysis unit 126 analyzes whether the power supply pattern to which the power supply pin of interest in the data extraction unit 121 is connected is a surface wiring, and determines whether the power supply pattern is a surface wiring. (Step S12: YES), the process proceeds to step S13. Otherwise (step S12: NO), the process proceeds to step S5 of the layout check process described in the first embodiment.

  In step S13, the power supply island determining unit 125 determines whether the size of the surface of the power supply pattern is equal to or smaller than a threshold. When the power supply pattern is equal to or less than the threshold value (step S13: YES), the power supply pattern is determined to be a “power supply island” (step S14). Otherwise (step S13: NO), the power supply pattern is determined to be a main power supply plane. A determination is made (step S15).

If it is determined in step S14 that the power supply pattern is “power supply island”, the connection information analysis unit 126 determines whether there is a wiring connecting the “power supply island” and the main power supply plane without using a bypass capacitor. The analysis is performed (step S16).
If there is a wire connecting the "power island" and the main power plane without the intermediary of the bypass capacitor (step S16: YES), it is determined that an error has occurred (step S17), and if no such wire exists (step S17). S16: NO), and proceeds to step S5.

If it is determined in step S15 that the power supply pattern is the main power supply plane, it is determined that an error has occurred (step S17), and the process proceeds to step S5.
When the layout check processing is performed on the PCB layout shown in FIG. 11, in step S16, the power supply pattern 351 that directly connects the “power supply island” 1102 and the main power supply pattern 1101 without using a bypass capacitor is analyzed by the connection information analysis unit 126. Is detected, it is determined that an error has occurred.

Specifically, the analysis performed by the connection information analysis unit 126 includes “power island” 1102 and graphic data (coordinate data representing a graphic) of a main power pattern, and coordinates of two power vias provided on the power pattern 351. It is checked whether the coordinates of the two power supply vias are respectively located in the area indicated by the graphic data of the “power supply island” 1102 and the area indicated by the graphic data of the main power supply pattern. Since the power supply pattern 351 corresponds to such a power supply pattern, it is determined that an error has occurred.
<Supplement>
It is needless to say that the present invention is not limited to the above-described embodiment and modifications. The following cases are also included in the present invention.
(1) The layout check process described in the first embodiment is performed even when an error is determined in the connection relationship between a certain power supply pin (referred to as a first power supply pin) and a certain bypass capacitor (referred to as a first bypass capacitor). The connection relationship between another power supply pin and the first bypass capacitor is checked. If the connection relationship between the first power supply pin and the first bypass capacitor is determined to be an error, the first bypass capacitor is thereafter checked. And the layout check processing may be speeded up.
(2) In the first embodiment, the power pin of the component to be checked is described as the power pin of the high-speed IC. However, the power pin of the connector or the component specified by the user may be checked.

Further, in the first embodiment, the power supply pin to be checked and the bypass capacitor are combined and brute-forced for checking, but the combination of the power supply pin and the bypass capacitor may be specified by the user.
(3) The bypass capacitors to be checked may be divided into high-frequency bypass capacitors and low-frequency bypass capacitors in consideration of the impedance characteristics of the capacitors, and the check targets may be selected and extracted.
(4) In the first embodiment, the error information is output to the display unit 14. However, the output destination may be the storage unit 13, or if the layout check system 1 is connected to a network, the output destination is Other external devices connected to the network may be used.
(5) In the first embodiment, the wiring path distance between the power supply pin and the power supply via is set as Z1, and the wiring distance between the power supply pin and the bypass capacitor is set as Z2. If Z1 <Z2, an error is determined. May be determined to be an error when Z1 + α <Z2. In this case, the specific value α may be a value input by the user, or may be a specified value of the system.
(6) The present invention may be a layout check method including each procedure of the above-described layout check processing (the procedures shown in FIGS. 5, 6, 7, and 15 and the like). It may be a program to be performed by the user. Further, it may be a digital signal composed of the program.
(7) The present invention provides a computer-readable recording medium for the program or the digital signal, for example, a flexible disk, a hard disk, a CD-ROM, an MO, a DVD, a DVD-ROM, a DVD-RAM, and a BD (Blu-ray Disc). ), And may be recorded in a semiconductor memory or the like.
(8) In the present invention, the program or the digital signal may be transmitted via a network such as an electric communication line, a wireless or wired communication line, or the Internet.
(9) According to the present invention, the program or the digital signal may be recorded on the recording medium and transferred, or the control program or the digital signal may be transferred via the network or the like to provide an independent program. May be implemented in the computer system.

  The layout check system according to the present invention relates to a method for determining whether or not a PCB layout defined by layout data created by using a CAD system or the like is a layout for effectively functioning a bypass capacitor arranged on the PCB. This is very useful because the check can be performed more accurately than the conventional check system described in the prior art.

FIG. 2 is a diagram illustrating a functional configuration of a layout check system according to the first embodiment; FIG. 6 is a diagram illustrating an example of a PCB layout to be checked for layout. FIG. 3 is a diagram schematically illustrating a cross section when the PCB of the PCB layout illustrated in FIG. 2 is divided by the power supply pattern 302. FIG. 3 is a diagram illustrating an example of an equivalent circuit of an impedance value Z1 and an impedance value Z2. FIG. 5 is a flowchart for explaining a layout check process according to the first embodiment; FIG. 5 is a flowchart for explaining a layout check process according to the first embodiment; FIG. 5 is a flowchart for explaining a layout check process according to the first embodiment; It is a figure showing an example of list information on an extracted power pin. It is a figure showing an example of list information of an extracted bypass capacitor. FIG. 4 is a diagram illustrating an example of wiring information. FIG. 5 is a diagram illustrating an example of a graph of impedance values Z1 and Z2 that change according to frequency. FIG. 12 is a graph in which a graph of Z1 / Z2 values is added to FIG. FIG. 13 is a diagram illustrating a functional configuration of a layout check unit according to the second embodiment. FIG. 4 is a diagram illustrating an example of a PCB layout to be checked for layout. FIG. 13 is a flowchart for explaining a layout check process according to the second embodiment;

Explanation of reference numerals

Reference Signs List 1 layout check system 9 data input unit 10 command input unit 11 layout data creation unit 12, 12A layout check unit 13 storage unit 14 display unit 121 data extraction unit 122 calculation unit 123 determination unit 124 error information output unit 125 power supply island determination unit 126 Connection information analysis unit

Claims (7)

A layout check system for checking layout data defining a layout of a power supply on a printed wiring board, a component having a power supply pin, and a bypass capacitor,
The information including a base value for calculating a first value that is a value corresponding to the impedance between the power supply pin and the power supply and a second value that is a value corresponding to the impedance between the power supply pin and the bypass capacitor. Storage means for storing layout data;
Calculating means for calculating the first value and the second value based on the stored layout data;
Determining means for comparing the calculated values of the first value and the second value to determine whether or not the layout is a layout for effectively operating the bypass capacitor;
An output unit that outputs error information when a negative determination is made by the determination unit. The calculation means calculates a first value that is a shortest wiring distance between the power supply pin and the power supply and a second value that is a shortest wiring distance between the power supply pin and the bypass capacitor based on the layout data. ,
The said determination means determines that the said layout is not the layout which makes the said bypass capacitor function effectively, when the said 1st value is smaller than the said 2nd value. Layout check system. When a power supply via is provided on a wiring to which the power supply pin and the bypass capacitor are connected,
The calculating means calculates a first value that is a shortest wiring distance between the power supply pin and the power supply via and a second value that is a shortest wiring distance between the power supply pin and the bypass capacitor based on the layout data. The layout check system according to claim 2, wherein: The storage means stores a threshold value,
The determination unit compares the stored threshold value with the value of the ratio of the second value to the first value, and determines that the layout is a layout that allows the bypass capacitor to function effectively. The layout check system according to claim 1, wherein it is determined whether or not the layout check is performed. The layout data includes wiring type information for identifying whether the wiring is a line or a surface, and for the surface wiring, size information indicating an area size is included.
The storage means stores a specified value,
The layout check system further includes:
Analysis means for analyzing whether or not the wiring connecting the power supply pin and the capacitor is a surface wiring based on the wiring type information;
As a result of the analysis, if it is found that the wiring connecting the power supply pin and the capacitor is a surface wiring, the area size of the wiring on the surface is referred to the size information, and the stored prescribed value is stored. Power supply plane determining means for determining whether or not the power supply plane is equal to or less than a specified value, and determining that the wiring on the surface is a specific power supply plane if the value is equal to or less than a specified value,
When the power supply plane determining means determines that the wiring on the surface connecting the power supply pin and the capacitor is a specific power supply plane, the analysis means further includes the specific power supply plane based on the layout data. And whether or not the power supply is connected without passing through the bypass capacitor.As a result, when it is found that the specific power supply plane and the power supply are connected without passing through the bypass capacitor, the layout The layout check system according to claim 1, wherein it is determined that the layout does not have a layout that allows the bypass capacitor to function effectively. A layout check method for checking layout data defining a layout of a power supply on a printed wiring board, a component having a power supply pin, and a bypass capacitor,
Layout including information serving as a basis for calculating a first value corresponding to an impedance between the power supply pin and the power supply and a second value corresponding to an impedance between the power supply pin and the bypass capacitor An acquisition step for acquiring data;
A calculating step of calculating the first value and the second value based on the layout data;
A determining step of comparing the calculated values of the first value and the second value to determine whether the layout is a layout that effectively functions the bypass capacitor;
An output step of outputting error information when a negative determination is made in the determination step. A program for causing a computer to perform a layout check process for checking layout data defining a layout of a power supply on a printed wiring board, a component having a power supply pin, and a bypass capacitor,
The layout check processing includes:
Layout including information serving as a basis for calculating a first value corresponding to an impedance between the power supply pin and the power supply and a second value corresponding to an impedance between the power supply pin and the bypass capacitor An acquisition step for acquiring data;
A calculating step of calculating the first value and the second value based on the layout data;
A determining step of comparing the calculated values of the first value and the second value to determine whether the layout is a layout that effectively functions the bypass capacitor;
An output step of outputting error information when a negative determination is made in the determination step.

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